ISL6532A

FN9099 Rev 6.00

Page 7 of 18

Sep 12, 2013

STATE LOGIC

S3# Transition Level

-1.5

-

V

S5# Transition Level

-1.5

-

V

PWM CONTROLLER GATE DRIVERS

UGATE and LGATE Source

--0.8

-

A

UGATE and LGATE Sink

-0.8

-

A

NCH BACKFEED CONTROL

NCH Current Sink

NCH = 0.8V

-

-

6

mA

NCH Trip Level

9.0

9.5

10.0

V

VDDQ STANDBY LDO

Output Drive Current

P5VSBY = 5.0V

-

-

650

mA

P5VSBY = 3.3V

-

-

550

mA

VTT REGULATOR

Upper Divider Impedance

-2.5

-

k



Lower Divider Impedance

-2.5

-

k



VREF_OUT Buffer Source Current

--

2mA

Periodic load applied with 30% duty cycle

and 10ms period using ISL6532AEVAL1

evaluation board (see Application Note

AN1056)

-3

-

3

A

LINEAR REGULATOR

DC GAIN

Note 3

-

80

-

dB

Gain Bandwidth Product

GBWP

Note 3

9

-

-

MHz

Slew Rate

SR

Note 3

-

6

-

V/

s

DRIVE2 High Output Voltage

10.0

10.2

-

V

DRIVE2 Low Output Voltage

-

0.16

0.40

V

DRIVE2 High Output Source Current

-.5

-1.4

-

mA

DRIVE2 Low Output Sink Current

.85

1.3

-

mA

PGOOD

PGOOD Rising Threshold

-

57.5

-

%

PGOOD Falling Threshold

-

45.0

-

%

PROTECTION

OCSET Current Source

15

20

22.5

A

VDDQ OV Level

S0

-

115

-

%

VDDQ UV Level

S0

-

85

-

%

Linear Regulator OV Level

S0

-

115

-

%

Linear Regulator UV Level

S0

-

85

-

%

Thermal Shutdown Limit

Note 3

-

140

-

°C

and Simplified Power System Diagrams and Typical Application Schematics (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS