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ISL6532BCR Datasheet(PDF) 10 Page - Renesas Technology Corp

Part # ISL6532BCR
Description  ACPI Regulator/Controller for Dual Channel DDR Memory Systems
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL6532BCR Datasheet(HTML) 10 Page - Renesas Technology Corp

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ISL6532B
FN9120 Rev 3.00
Page 10 of 15
Jul 2004
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL6532B
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections with
vias to this layer. Dedicate another solid layer as a power
plane and break this plane into smaller islands of common
voltage levels. Keep the metal runs from the PHASE terminals
to the output inductor short. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the GATE pins to the MOSFET
gates should be kept short and wide enough to easily handle
the 1A of drive current.
In order to dissipate heat generated by the internal VTT LDO,
the ground pad, pin 21, should be connected to the internal
ground plane through at least four vias. This allows the heat to
move away from the IC and also ties the pad to the ground
plane through a low impedance path.
The switching components should be placed close to the
ISL6532B first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin
with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The PWM
wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage
VOSC.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6532B) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide a
closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin is
the difference between the closed loop phase at f0dB and 180
degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
VDDQ
5VSBY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
LOUT
COUT1
CIN
VIN_DDR
KEY
COMP
ISL6532B
UGATE
R4
R2
CBP
FB
GND
5VSBY
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
R1
C2
VIA CONNECTION TO GROUND PLANE
Q1
R3
C3
C1
Q2
12VATX
CBP
GND
P12V
LGATE
P5VSBY
VDDQ(2)
VTT(2)
COUT2
VDDQ
VTT
NCH
GND PAD
FLC
1
2
 x LO x CO
-------------------------------------------
=
FESR
1
2
 x ESR x CO
--------------------------------------------
=


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