ISL6614

FN9155 Rev.5.00

Page 10 of 12

May 5, 2008

the SO14 package is approximately 1W at room temperature,

while the power dissipation capacity in the QFN packages, with

an exposed heat escape pad, is around 2W. See “Layout

Considerations” on page 10 for thermal transfer improvement

suggestions. When designing the driver into an application, it is

recommended that the following calculation is used to ensure

safe operation at the desired frequency for the selected

MOSFETs. The total gate drive power losses due to the gate

charge of MOSFETs and the driver’s internal circuitry and their

corresponding average driver current can be estimated using

Equations 2 and 3, respectively:

upper and lower MOSFETs, respectively; PVCC is the drive

voltages for both upper and lower FETs, respectively. The

capacitive load and is typically 200mW at 300kHz.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate resistors

of MOSFETs. Figures 3 and 4 show the typical upper and

lower gate drives turn-on transition path. The power dissipation

on the driver can be roughly estimated as:

Layout Considerations

For heat spreading, place copper underneath the IC whether it

has an exposed pad or not. The copper area can be extended

beyond the bottom area of the IC and/or connected to buried

copper plane(s) with thermal vias. This combination of vias for

vertical heat escape, extended copper plane, and buried

planes for heat spreading allows the IC to achieve its full

thermal potential.

Place each channel power component as close to each other

as possible to reduce PCB copper losses and PCB parasitics:

shortest distance between DRAINs of upper FETs and

SOURCEs of lower FETs; shortest distance between DRAINs

of lower FETs and the power ground. Thus, smaller amplitudes

of positive and negative ringing are on the switching edges of

the PHASE node. However, some space in between the power

components is required for good airflow. The traces from the

drivers to the FETs should be kept short and wide to reduce the

inductance of the traces and to promote clean drive signals.







++

=

(EQ. 2)







=







=



------------------------------



------------------------------

+









+



=

(EQ. 3)

2P



DR_UP

2P



DR_LOW



++

=

(EQ. 4)

+

--------------------------------------

+

----------------------------------------

+





2

---------------------



=

+

--------------------------------------

+

----------------------------------------

+





2

---------------------



=

-------------

+

=

-------------

+

=

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Q1

D

S

G

BOOT

PHASE

PVCC

PVCC

Q2

D

S

G