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ISL6620A Datasheet(PDF) 7 Page - Renesas Technology Corp |
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ISL6620A Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 10 page ISL6620, ISL6620A FN6494 Rev 0.00 Page 7 of 10 April 25, 2008 driver is enabled and the PWM input signal takes control of the gate drives. If VCC drops below the falling threshold of 3.5V (typically), operation of the driver is disabled. Internal Bootstrap Device ISL6620, ISL6620A features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the PHASE node. This reduces voltage stress on the BOOT to PHASE pins. The bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for VCC. Its capacitance value can be estimated using Equation 1: where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. Select results are exemplified in Figure 2. Power Dissipation Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the layout resistance, and the selected MOSFET’s internal gate resistance and total gate charge (QG). Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level may push the IC beyond the maximum recommended operating junction temperature. The DFN package is more suitable for high frequency applications. See “Layout Considerations” on page 8 for thermal impedance improvement suggestions. The total gate drive power losses due to the gate charge of MOSFETs and the driver’s internal circuitry and their corresponding average driver current can be estimated using Equations 2 and 3, respectively: where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1 and VGS2) in the corresponding MOSFET data sheet; IQ is the driver’s total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively; UVCC and LVCC are the drive voltages for both upper and lower FETs, respectively. The IQ*VCC product is the quiescent power of the driver without a load. The total gate drive power losses are dissipated among the resistive components along the transition path, as outlined in Equation 4. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on current paths. 20nC FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE VBOOT_CAP (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 QGATE = 100nC 50nC CBOOT_CAP QGATE V BOOT_CAP -------------------------------------- QGATE QG1 VCC VGS1 ------------------------------- NQ1 = (EQ. 1) FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PQg_TOT PQg_Q1 PQg_Q2 IQ VCC ++ = (EQ. 2) PQg_Q1 QG1 UVCC2 VGS1 --------------------------------------- FSW NQ1 = PQg_Q2 QG2 LVCC2 VGS2 -------------------------------------- FSW NQ2 = IDR QG1 UVCC NQ1 VGS1 ------------------------------------------------------ QG2 LVCC NQ2 VGS2 ----------------------------------------------------- + FSW IQ + = (EQ. 3) PDR PDR_UP PDR_LOW IQ VCC ++ = (EQ. 4) PDR_UP RHI1 RHI1 REXT1 + -------------------------------------- RLO1 RLO1 REXT1 + ---------------------------------------- + PQg_Q1 2 --------------------- = PDR_LOW RHI2 RHI2 REXT2 + -------------------------------------- RLO2 RLO2 REXT2 + ---------------------------------------- + PQg_Q2 2 --------------------- = REXT1 RG1 RGI1 NQ1 ------------- + = REXT2 RG2 RGI2 NQ2 ------------- + = Q1 D S G RG1 RL1 BOOT RHI1 CDS CGS CGD RLO1 PHASE UVCC |
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