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ISL6843IUZ Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # ISL6843IUZ
Description  Improved Industry Standard Single-Ended Current Mode PWM Controller
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL6843IUZ Datasheet(HTML) 9 Page - Renesas Technology Corp

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ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
FN9124 Rev 13.00
Page 9 of 14
February 18, 2015
Pin Descriptions
RTCT - This is the oscillator timing control pin. The operational
frequency and maximum duty cycle are set by connecting a
resistor, RT, between VREF and this pin and a timing capacitor,
CT, from this pin to GND. The oscillator produces a sawtooth
waveform with a programmable frequency range up to
2.0MHz. The charge time, tC, the discharge time, tD, the
switching frequency, f, and the maximum duty cycle, Dmax,
can be calculated from Equations 1, 2, 3 and 4:
Figure 4 may be used as a guideline in selecting the capacitor
and resistor values required for a given frequency.
COMP - COMP is the output of the error amplifier and the input
of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
FB - The output voltage feedback is connected to the inverting
input of the error amplifier through this pin. The non-inverting
input of the error amplifier is internally tied to a reference
voltage.
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0V to 1.0V and has
an internal offset of 100mV.
GND - GND is the power and small signal reference ground for
all functions.
OUT - This is the drive output to the power switching device. It
is a high current output capable of driving the gate of a power
MOSFET with peak currents of
1.0A.
VDD - VDD is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
IDD current is the sum of the operating current and the average
output current. Knowing the operating frequency, f, and the
MOSFET gate charge, Qg, the average output current can be
calculated in Equation 5:
To optimize noise immunity, bypass VDD to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass to
GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Functional Description
Features
The ISL684x current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts, it
is the obvious choice for new designs or existing designs which
require updating.
Oscillator
The ISL684x family of controllers have a sawtooth oscillator
with a programmable frequency range to 2MHz, which can be
programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Figure 4 for the resistor
and capacitance required for a given frequency.)
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated in Figure 5, clamps the voltage on COMP.
Gate Drive
The ISL684x family are capable of sourcing and sinking 1A
peak current. To limit the peak current through the IC, an
optional external resistor may be placed between the
totem-pole output of the IC (OUT pin) and the gate of the
MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale current
feedback signal. For applications where the duty cycle is
greater than 50%, slope compensation is required to prevent
instability. The minimum amount of slope compensation
required corresponds to 1/2 the inductor downslope. Adding
excessive slope compensation, however, results in a control
loop that behaves more as a voltage mode controller than as a
current mode controller.
Slope compensation may be added to the CS signal shown in
Figure 7.
tC 0.583 RT CT
(EQ. 1)
tD RT
CT
0.0083 RT 4.3
0.0083 RT 2.4
----------------------------------------------


ln
(EQ. 2)
f
1tC tD
+

=
(EQ. 3)
DtC f
=
(EQ. 4)
(EQ. 5)
IOUT
Qg f
=
FIGURE 5. SOFT-START
VREF
COMP
GND


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