SP5610

4

FUNCTIONAL DESCRIPTION

Clock are fed in on the SDA and SCL lines respectively as

accept new data (write mode) or send data (read mode). The

LSB of the address byte (R/W) sets the device into write mode

if it is low and read mode if it is high. The Tables in Fig. 3

illustrate the format of the data. The device can be

programmed to respond to several addresses, which enables

Table 4 shows how the address is selected by applying a

voltage to P3. When the device receives a correct address

byte, it pulls the SDA line low during the acknowledge period,

and during following acknowledge periods after further data

bytes are programmed. When the device is programmed into

the read mode, the controller accepting the data must pull the

SDA line low during all status byte acknowledge periods to

read another status byte. If the controller fails to pull the SDA

line low during this period, the device generates an internal

STOP condition, which inhibits further reading.

WRITE MODE (Frequency Synthesis)

When the device is in write mode bytes 2+3 select the

synthesised frequency, while bytes 4+5 control the output port

states, charge pump, reference divider ratio and various test

modes.

Once the correct address is received and acknowledged,

the first bit of the next byte determines whether that byte is

interpreted as byte 2 or 4; a logic 0 for frequency information

and a logic 1 for control and output port information. When byte

2 is received the device always expects byte 3 next. Similarly,

when byte 4 is received the device expects byte 5 next.

Additional data bytes can be entered without the need to

recognised. This allows a smooth frequency sweep for fine

tuning or AFC purposes.

If the transmission of data is stopped mid–byte (e.g. by

another device on the bus) then the previously programmed

byte is maintained.

Frequency data from bytes 2 and 3 is stored in a 15–bit

register and is used to control the division ratio of the 15–bit

programmable divider. This is preceded by a divide–by–8

prescaler and amplifier to give excellent sensitivity at the local

oscillator input, see Fig. 5. The input impedance is shown in

Fig. 7.

The programmed frequency can be calculated by

multiplying the programmed division ratio by 8 times the

When frequency data is entered, the phase comparator, via

a charge pump and varicap drive amplifier, adjusts the local

oscillator control voltage until the output of the programmable

divider is frequency and phased locked to the comparison

frequency.

The reference frequency may be generated by an external

source capacitively coupled into pin 2, or provided by an

on–board crystal controlled oscillator. The comparison

the reference divider. The reference divider division ratio is

switchable from 512 to 1024, and is controlled by bit 7 of byte

4 (TS0); a logic 1 for 512; a logic 0 for 1024. The SP5610 differs

from the SP5510 in this respect, only 512 being available on

the SP5510. Note, the comparison frequency is 7.8125kHz

when a 4MHz reference is used, and divide by 512 is selected.

Bit 2 of byte 4 of the programming data (CP) controls the

current in the charge pump circuit, a logic 1 for

"170mA and

a logic 0 for

"50mA allowing compensation for the variable

tuning slope of the tuner and also to enable fast channel

changes over the full band. When the device is ‘frequency

locked’ the charge pump current is internally set to

"50mA

regardless of CP.

Bit 4 of byte 4 (T0) disables the charge pump when it is set

to a logic 1.

Bit 8 of byte 4 (OS) switches the charge pump drive

amplifier’s output off when it is set to a logic 1.

Bit 3 of byte 4 (T1) enables various test modes when set

high. These modes are selected by bits 5, 6, 7 of byte 4 (TS2,

TS1, TS0) as detailed in Table 5. When T1 is set low, TS2 and

TS1 are assigned a ‘don’t care’ condition, and TS0 selects the

reference divider ratio as previously described.

Byte 5 programs the output ports P3 to P7; a logic 0 for a

high impedance output and a logic 1 for low impedance (on).

READ MODE

When the device is in read mode the status byte read from

the device on the SDA line takes the form shown in Table 2.

Bit 1 (POR) is the power–on reset indicator and is set to a

(at 25

°C), e.g. when the device is initially turned on. The POR

is reset to 0 when the read sequence is terminated by a stop

programmed information is lost and the output ports are all set

to high impedance.

Bit 2 (FL) indicates whether the device is phase locked, a

logic 1 is present if the device is locked, and a logic 0 if the

device is unlocked.

Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7,

P5 and P4 respectively. A logic 0 indicates a low level and a

logic 1 a high level. If the ports are to be used as inputs they

should be programmed to a high impedance state (logic 1).

These inputs will then respond to data complying with TTL

type voltage levels.

Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of

the 5 level ADC. The ADC can be used to feed AFC

information to the microprocessor from the IF section of the

receiver, as illustrated in the typical application circuit.

APPLICATION

A typical application is shown in Fig. 4. All input/output

interface circuits are shown in Fig. 6. The SP5610 is function

and pin equivalent to the SP5510 device apart from the

switchable reference divider, and has much lower power

dissipation, improved RF sensitivity and better ESD

performance.