ISL6269A

FN9253 Rev 3.00

Page 8 of 15

November 18, 2014

PVCC (Pin 12)

The PVCC pin is the input voltage bias for the LG low-side

MOSFET gate driver. Connect +5V from the PVCC pin to the PGND

pin. Decouple with at least 1µF of an MLCC capacitor across the

PVCC and PGND pins.

BOOT (Pin 13)

The BOOT pin stores the input voltage for the UG high-side

MOSFET gate driver. Connect an MLCC capacitor across the BOOT

and PHASE pins. The boot capacitor is charged through an

internal boot diode connected from the PVCC pin to the BOOT pin,

each time the PHASE pin drops below PVCC minus the voltage

dropped across the internal boot diode.

UG (Pin 14)

The UG pin is the output of the high-side MOSFET gate driver.

Connect to the gate of the high-side MOSFET.

PHASE (Pin 15)

The PHASE pin detects the voltage polarity of the PHASE node

and is also the current return path for the UG high-side MOSFET

gate driver. Connect the PHASE pin to the node consisting of the

high-side MOSFET source, the low-side MOSFET drain and the

output inductor.

PGOOD (Pin 16)

The PGOOD pin is an open-drain output that indicates when the

converter is able to supply regulated voltage. Connect the PGOOD

pin to +5V through a pull-up resistor.

Theory of Operation

Modulator

The ISL6269A is a hybrid of fixed frequency PWM control, and

variable frequency hysteretic control. Intersil’s R3™ Technology

can simultaneously affect the PWM switching frequency and

PWM duty cycle in response to input voltage and output load

transients. The term “Ripple” in the name “Robust Ripple

Regulator” refers to the converter output inductor ripple current,

not the converter output ripple voltage. The R3™ Modulator

result of charge and discharge current through a ripple capacitor

threshold voltage. Figure 3 shows PWM pulses being generated

switching frequency is proportional to the slew rates of the

Power-On Reset

The controller will become once again disabled when the voltage

EN, Soft-Start and PGOOD

The ISL6269A uses a digital soft-start circuit to ramp the output

voltage of the converter to the programmed regulation setpoint

at a predictable slew rate. The slew rate of the soft-start

sequence has been selected to limit the in-rush current through

the output capacitors as they charge to the desired regulation

voltage. When the EN pin is pulled above the rising EN threshold

output voltage begins to rise. The output voltage enters regulation

in approximately 1.5ms and the PGOOD pin goes to high

The PGOOD pin indicates when the converter is capable of

supplying regulated voltage. The PGOOD pin is an undefined

 V

IN

–





=

(EQ. 1)



=

(EQ. 2)

Ripple Capacitor Voltage CR

Error Amplifier Voltage VCOMP

Window Voltage VW

PWM

FIGURE 3. MODULATOR WAVEFORMS DURING LOAD TRANSIENT

EN

VCC and PVCC

VOUT

PGOOD

1.5ms

2.75ms

FIGURE 4. SOFT-START SEQUENCE