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ISL6564IR Datasheet(PDF) 10 Page - Renesas Technology Corp |
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ISL6564IR Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 28 page  ISL6564 FN9156 Rev 2.00 Page 10 of 28 Dec 27, 2004 Functional Pin Description VCC Supplies all the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply or through a series 300 resistor to a +12V supply. GND Bias and reference ground for the IC. EN This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN is driven above 1.29V, the ISL6564 is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN below 1.16V will clear all fault states and prime the ISL6564 to soft-start when re-enabled. ENLL This pin is a logic-level enable input for the controller. When asserted to a logic high, the ISL6564 is active depending on status of EN, the internal POR, VID inputs and pending fault states. Deasserting ENLL will clear all fault states and prime the ISL6564 to soft-start when re-enabled. When floating, ENLL pin will be pulled to high internally with a typical voltage as 1.15V. FS A resistor, RT, placed from FS to ground will set the switching frequency. There is an inverse relationship between the value of the resistor and the switching frequency. See Figure 15 and Equation 29. VID5, VID4, VID3, VID2, VID1, and VID0 These are the inputs to the internal DAC that provides the reference voltage for output regulation. Connect these pins either to open-drain outputs with or without external pull-up resistors or to active-pull-up outputs. VID5-VID0 have 45µA internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. These inputs can be pulled up as high as VCC plus 0.3V. VDIFF, VSEN, and RGND VSEN and RGND form the precision differential remote- sense amplifier. This amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier’s output and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote load. FB and COMP Inverting input and output of the error amplifier, respectively. FB is connected to VDIFF through a resistor. A negative current, proportional to output current is present on the FB pin. A properly sized resistor between VDIFF and FB sets the load line (droop). The droop scale factor is set by the ratio of the ISEN resistors and the lower MOSFET rDS(ON). COMP is tied back to FB through an external R-C network with no DC connection to compensate the regulator. DAC and REF The DAC output pin is the output of the precision internal DAC reference. The REF input pin is the positive input of the Error Amp. In typical applications, a 1k , 1% resistor is used between DAC and REF to generate a precise offset voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™ operations. PWM1, PWM2, PWM3, PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Leave PWM4 unconnected and tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. Tie both PWM4 and PWM3 to high for 1-phase operation. ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4- The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used as a reference for channel balancing, protection, and regulation. Inactive channels should have their respective sense inputs left open (for example, for 3-phase operation open ISEN4+). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional to the inductor current. The sensed current is proportional to the output current, and scaled by the DCR of the inductor, divided by RISEN. When configured for rDS(ON) current sensing, the ISEN1-, ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lower MOSFET sources. The ISEN1+, ISEN2+, ISEN3+, and ISEN4+ pins are then held at a virtual ground, such that a resistor connected between them, and the drain terminal of the associated lower MOSFET, will carry a current proportional to the current flowing through that channel. The current is determined by the negative voltage developed across the lower MOSFET’s rDS(ON), which is the channel current scaled by rDS(ON). |
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