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A43E26161G-95 Datasheet(PDF) 10 Page - AMIC Technology |
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A43E26161G-95 Datasheet(HTML) 10 Page - AMIC Technology |
10 / 10 page A43E26161 (December, 2004, Version 1.0) 9 AMIC Technology, Corp. Mode Register Filed Table to Program Modes Register Programmed with MRS Address BS1 BS0 A11,A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function 0 0 RFU W.B.L TM CAS Latency BT Burst Length (Note 3) (Note 1) (Note 2) Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1 Vendor Use Only 0 1 1 3 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved 0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 256(Full) Reserved Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle. 2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled. 3. BS0, BS1 must be 0,0 to select the Mode Register (vs. the Extended Mode Register). Extended Mode Register Table BS1 BS0 A11, A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 0 All have to be set to “0” DS TCSR PASR (Note) Driver Strength Temperature-Compensated Self-Refresh: Partial-Array Self Refresh: Driver Strength A4 A3 Max. Case Temp. A6 A5 Driver Strength 0 0 70 °C A2 A1 A0 Banks to be Self-Refreshed 0 0 Full 0 1 45 °C 0 0 0 All banks 0 1 1/2 1 0 15 °C 0 0 1 Bank A, Bank B 1 0 1/4 1 1 85 °C 0 1 0 Bank A 0 1 1 Reserved 1 0 0 Reserved 1 0 1 1/2 of Bank A 1 1 0 1/4 of Bank A 1 1 1 Reserved Note: BS1 and BS0 must be 1, 0 to select the Extended Mode Register (vs. the Mode Register) |
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