 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-21161NCCA-100 Datasheet(PDF) 3 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-21161NCCA-100 Datasheet(HTML) 3 Page - Analog Devices |
|
|
3 / 60 page  –3– REV. A ADSP-21161N TABLE OF CONTENTS GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3 ADSP-21161N Family Core Architecture . . . . . . . . . 5 SIMD Computational Engine . . . . . . . . . . . . . . . . 5 Independent, Parallel Computation Units . . . . . . . 5 Data Register File . . . . . . . . . . . . . . . . . . . . . . . . . 5 Single-Cycle Fetch of Instruction and Four Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data Address Generators With Hardware Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 5 ADSP-21161N Memory and I/O Interface Features . 5 Dual-Ported On-Chip Memory . . . . . . . . . . . . . . . 5 Off-Chip Memory and Peripherals Interface . . . . . 6 SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 Target Board JTAG Emulator Connector . . . . . . . 7 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Peripheral (Compatible) Interface . . . . . . . . 9 Host Processor Interface . . . . . . . . . . . . . . . . . . . . 9 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . 9 Program Booting . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Phase-Locked Loop and Crystal Double Enable . . 9 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Designing an Emulator-Compatible DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . 10 Additional Information . . . . . . . . . . . . . . . . . . . . . . 11 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 12 BOOT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 19 ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 19 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 20 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-up Sequencing – Silicon Revision 0.3, 1.0, 1.1 . . . . . . . . . . . . . . . . . . . . 22 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory Read – Bus Master . . . . . . . . . . . . . . . . 27 Memory Write – Bus Master . . . . . . . . . . . . . . . . 28 Synchronous Read/Write – Bus Master . . . . . . . . 29 Synchronous Read/Write – Bus Slave . . . . . . . . . . 30 Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous Read/Write – Host to ADSP-21161N . . . . . . . . . . . . . . . . . . 33 Three-State Timing – Bus Master, Bus Slave . . . . 35 DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 37 SDRAM Interface – Bus Master . . . . . . . . . . . . . 39 Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SPI Interface Specifications . . . . . . . . . . . . . . . . . 47 JTAG Test Access Port and Emulation . . . . . . . . 50 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 51 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 51 Output Disable Time . . . . . . . . . . . . . . . . . . . . . 51 Example System Hold Time Calculation . . . . . . . 51 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 52 Environmental Conditions . . . . . . . . . . . . . . . . . . . 52 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 52 225-BALL METRIC MBGA PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . 53 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 55 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 55 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 GENERAL DESCRIPTION The ADSP-21161N SHARC DSP is the first low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARCs in SISD (Single Instruction, Single Data) mode. Like other SHARC DSPs, the ADSP-21161N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21161N includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks. As was first offered in the ADSP-21160, the ADSP-21161N offers a Single-Instruction-Multiple-Data (SIMD) architecture. Using two computational units (ADSP-2106x SHARCs have one), the ADSP-21161N can double cycle performance versus the ADSP-2106x on a range of DSP algorithms. Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21161N has a 10 ns instruction cycle time. With its SIMD computational hardware running at 100 MHz, the ADSP-21161N can perform 600 million math operations per second. Table 1 shows performance benchmarks for the ADSP-21161N. Table 1. Benchmarks (at 100 MHz) Benchmark Algorithm Speed (at 100 MHz) 1024 Point Complex FFT (Radix 4, with reversal) 171 µs FIR Filter (per tap) 1 5 ns IIR Filter (per biquad) 1 40 ns 1 1 Specified in SISD mode. Using SIMD, the same benchmark applies for two sets of computations. For example, two sets of biquad operations can be performed in the same amount of time as the SISD mode benchmark. Matrix Multiply (pipelined) [3 × 3] × [3 × 1] 30 ns [4 × 4] × [4 × 1] 37 ns Divide (y/x) 60 ns 1 Inverse Square Root 40 ns 1 DMA Transfers 800 M bytes/s |
Similar Part No. - ADSP-21161NCCA-100 |
|
Similar Description - ADSP-21161NCCA-100 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
