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ADSP-21364SBSQ-ENG Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-21364SBSQ-ENG Datasheet(HTML) 8 Page - Analog Devices |
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8 / 52 page  Rev. PrB | Page 8 of 52 | September 2004 ADSP-21364 Preliminary Technical Data Timers The ADSP-21364 has a total of four timers: a core timer able to generate periodic software interrupts and three general purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: • Pulse Waveform Generation mode • Pulse Width Count /Capture mode • External Event Watchdog mode The core timer can be configured to use FLAG3 as a Timer Expired signal, and each general-purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables all three general purpose timers independently. Program Booting The internal memory of the ADSP-21364 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave or an internal boot. Booting is determined by the Boot Configuration (BOOTCFG1–0) pins (see Table 6 on Page 14). Selection of the boot source is controlled via the SPI as either a master or slave device. Phase-Locked Loop The ADSP-21364 uses an on-chip Phase-Locked Loop (PLL) to generate the internal clock for the core. On power up, the CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1 (see Table 7 on Page 14). After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 32 and soft- ware configurable divisor values of 1, 2, 4, 8, and 16. Power Supplies The ADSP-21364 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply (AVDD) powers the ADSP-21364’s clock generator PLL. To produce a stable clock, programs should provide an external circuit to filter the power input to the AVDD pin. Place the filter as close as possible to the pin. For an example circuit, see Figure 4. To prevent noise coupling, use a wide trace for the analog ground (AVSS) signal and install a decoupling capacitor as close as possible to the pin. Note that the AVSS and AVDD pins specified in Figure 4 are inputs to the processor and not the analog ground plane on the board. Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21364 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces- sor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro- priate “Emulator Hardware User's Guide”. DEVELOPMENT TOOLS The ADSP-21364 is supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® devel- opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21364. The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important fea- tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in com- plexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Sta- tistical profiling enables the programmer to non intrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and effi- ciently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints Figure 4. Analog Power (AVDD) Filter Circuit VDDINT AVDD AVSS 0.01 F 0.1 F 10 |
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