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ISL62871 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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ISL62871 Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 25 page  ISL62871, ISL62872 FN6707 Rev 1.00 Page 10 of 25 May 8, 2014 BOOT (Pin 18) Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin. VCC (Pin 19) Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1µF MLCC to the GND pin. See “Application Schematics” (Figures 2 and 3) on page 4. PVCC (Pin 20) Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10µF MLCC to the PGND pin. See “Application Schematics” (Figures 2 and 3) on page 4. ISL62871 Functional Pin Descriptions GND (Pin 1) IC ground for bias supply and signal reference. EN (Pin 2) Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the soft-start sequence. VID0 (Pin 3) Logic input for setpoint voltage selector. Use to select between the two setpoint reference voltages. External reference input when enabled by connecting the SET0 pin to the VCC pin. SREF (Pin 4) Soft-start and voltage slew-rate programming capacitor input. Setpoint reference voltage programming resistor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. See Figure 9 on page 12 for capacitor and resistor connections. SET0 (Pin 5) Voltage set-point programming resistor input. See Figure 9 on page 12 for resistor connection. PGOOD (Pin 6) Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. The pull-down resistance between the PGOOD pin and the GND pin identifies which protective fault has shut down the regulator. See Table 3 on page 16. FB (Pin 7) Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. The control loop compensation network connects between the FB pin and the converter output. See Figure 13 on page 17. VO (Pin 8) Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input for the overcurrent detection circuit. See Figure 10 on page 14. OCSET (Pin 9) Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this pin to the sense node. See Figure 10 on page 14. PHASE (Pin 10) Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3 modulator. Inductor current polarity detector input. Connect to junction of output inductor, high-side MOSFET, and low-side MOSFET. See “Application Schematics” (Figures 4 and 5) on page 5. UGATE (Pin 11) High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter. BOOT (Pin 12) Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin. VCC (Pin 13) Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1µF MLCC to the GND pin. See “Application Schematics” (Figures 4 and 5) on page 5. PVCC (Pin 14) Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10µF MLCC to the PGND pin. See “Application Schematics” (Figures 4 and 5) on page 5. LGATE (Pin 15) Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter. PGND (Pin 16) Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET. Setpoint Reference Voltage Programming Voltage identification (VID) pins select user-programmed setpoint reference voltages that appear at the SREF pin. The converter is in regulation when the FB pin voltage (VFB) equals the SREF pin voltage (VSREF.) The IC measures VFB and VSREF relative to the GND pin, not the PGND pin. The setpoint reference voltages use the naming convention VSET(x) where |
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