Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF


CA3338E Datasheet(PDF) 6 Page - Renesas Technology Corp

Part No. CA3338E
Description  CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters
Download  10 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo 

 
 6 page
background image
CA3338, CA3338A
FN1850 Rev 4.00
Page 6 of 10
July 2004
observed). VEE, which supplies the gate potential for the
output drivers, must be returned to a point at least as negative
as VREF-. Note that the maximum clocking speed decreases
when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to VREF- with an
input code of 00HEX (zero scale output), and an output equal to
255/256 of VREF+ (referred to VREF-) with an input code of
FFHEX (full scale output). The difference between the ideal and
actual values of these two parameters are the OFFSET and
GAIN errors, respectively; see Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full scale output - zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the ideal
step size (usually called an LSB). Also note that if the (-)
differential linearity error is less (in absolute numbers) than 1 LSB,
the device is monotonic. (The output will always increase for
increasing code or decrease for decreasing code).
If the code into an 8-bit D/A is at any value, say “N”, the output
voltage should be N/255 of the full scale output (referred to the
zero scale output). Any deviation from that output is an integral
linearity error, usually expressed in LSBs. See Figure 4.
Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to also
take these errors into account.
Dynamic Characteristics
Keeping the full-scale range (VREF+ - VREF-) as high as
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
delays. The VREF+ (and VREF- if bipolar) terminal should be
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7FHEX to 80HEX for an 8 bit device), and can be
measured by displaying the output as the input code alternates
around that point. The “glitch” energy is the area between the
actual output display and an ideal one LSB step voltage
(subtracting negative area from positive), at either the positive or
negative-going step. It is usually expressed in pV/s.
The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally weighted
resistors. This makes the “glitch” energy at each 1/8 scale
transition (1FHEX to 20HEX, 3FHEX to 40HEX, etc.) essentially
equal, and far less than the MSB transition would otherwise
display.
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160
 in parallel with the load
resistance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such as
Tektronix part number 131-0258-00 is recommended.
255/256
254/256
253/256
3/256
2/256
1/256
0
00
01
02
03
FD
FE
FF
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
OFFSET
ERROR
(SHOWN +)
GAIN ERROR
(SHOWN -)
INPUT CODE IN HEXADECIMAL (COMP = LOW)
FIGURE 3. D/A OFFSET AND GAIN ERROR
0
00
C
B
FROM “0” SCALE
INTEGRAL LINEARITY
ERROR (SHOWN -)
STRAIGHT LINE
TO FULL SCALE
VOLTAGE
INPUT CODE
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
A = IDEAL STEP SIZE (1/255 OF FULL
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
A
SCALE -“0” SCALE VOLTAGE)
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
ERROR




Html Pages

1  2  3  4  5  6  7  8  9  10 


Datasheet Download




Link URL

Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl