ISL1801

FN8259 Rev 1.00

Page 5 of 30

July 24, 2014

14

RPWM3

The reset signal for both flip-flops in the LATCHRPT circuit and overcurrent-protection circuit of DRIVE3/PHASE3. The

RPWM3=0 will reset both flip-flops. Avoid running PWM3=1 with RPWM3=0 for a long time or at very high frequency, since

it may result in very high switching frequency at DRIVE3 in the overcurrent protection condition.

15

BCMD

Logic input to control BDRIVE.

16

BRESET

Logic input to reset the LATCHRPT flip-flop in the BDRIVE control circuit.

17

WDI

Watchdog circuit clock input signal.

18

VDDREF

pins (CMP1O, AMPO) interfacing with the MCU.

19

LATCHRPT

Open drain output signal. When either comparator or Phase3 overcurrent protection is triggered, this pin is pulled LOW to

inform the MCU. The two internal flip-flops used to latch these faults can be reset by setting RWPM3=0.

20

PGOOD2

Open drain output pin indicating power-good for the low voltage regulator. A logic low signal at the watchdog output will also

pull this pin LOW allowing it to reset the MCU in either fault condition.

21

AMPO

Integrated amplifier output.

22

AMP-

Integrated amplifier inverting input.

23

AMP+

Integrated amplifier non-inverting input.

24

SGND

The ground pin of the sensitive control circuits biased by VCC5V. Connect this pin to a ground plane with minimum noise.

25

CMP1+

Comparator 1 non-inverting input.

26

CMP1-

Comparator 1 inverting input.

27

CMP1O

Comparator 1 output. This signal also triggers the flip-flop for the LATCHRPT signal.

28

CMP2-

Comparator 2 inverting input.

29

CMP2+

Comparator 2 non-inverting input.

30

FB2

The feedback sense pin for the low voltage switching regulator. The output voltage is programmable by a resistor divider

feeding back the output voltage.

31

TON2

On time adjustment for the secondary (low voltage) switching regulator. Connect a resistor from this pin to the input voltage

of the low voltage regulator to adjust the on time and switching frequency.

32

PGND2

The ground pin of the low voltage switching regulator’s power stage. There are switching power current pulses coming out of

this pin. Place the ground pad of the input power stage decoupling cap as close to this pin as possible.

33

PHASE2

The phase node of the low voltage switching regulator. This pin should be connected to the output inductor.

34

BOOT2

The boot pin of the low voltage switching regulator. An external bootstrap capacitor is required. This pin provides bias voltage

to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET.

The boot diode is included within the IC.

35

VIN2

Input of the low voltage switching regulator. This pin is connected to the drain of the internal high-side MOSFET.

36

VCC5V

The output of the internal 5V LDO providing the bias supply for the IC. A 1µF ceramic decoupling capacitor should be placed

from this pin to ground.

37

GND

The analog ground pin.

38

PRELOAD

successfully driven, the low voltage switching regulator will be enabled. If the PV module output power is insufficient, the low

voltage switching regulator will not start.

39

FB1

The feedback sense pin for the high voltage switching regulator. The output voltage is programmable by a resistor divider

feeding back the output voltage.

40

TON1

On time adjustment for the high voltage switching regulator. Connect a resistor from this pin to the input voltage of the high

voltage regulator to adjust the on time and switching frequency.

41

TIMER

Tie a resistor from VCC5V to this pin and a cap from this pin to ground. The RC time constant sets the time needed for both

start-up and watchdog timing. A minimum of 0.01µF should be connected to this pin to filter the switching noise from BOOT1.

The pull-up resistor should not be more than 200kΩ to assure correct operation.

PIN#

PIN NAME

DESCRIPTION