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ISL6263D Datasheet(PDF) 9 Page - Renesas Technology Corp |
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ISL6263D Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 18 page  ISL6263D FN6753 Rev 1.00 Page 9 of 18 July 8, 2010 Theory of Operation The R3 Modulator The heart of the ISL6263D is Intersil’s Robust-Ripple-Regulator (R3) Technology™. The R3 modulator is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control that will simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term “Ripple” in the name “Robust-Ripple-Regulator” refers to the synthesized voltage-ripple signal VR that appears across the internal ripple-capacitor CR. The VR signal is a representation of the output inductor ripple current. Transconductance amplifiers measuring the input voltage of the converter and the output set-point voltage VSOFT, together produce the voltage-ripple signal VR. A voltage window signal VW is created across the VW and COMP pins by sourcing a current proportional to gmVSOFT through a parallel network consisting of resistor RFSET and capacitor CFSET. The synthesized voltage-ripple signal VR along with similar companion signals are converted into PWM pulses. The PWM frequency is proportional to the difference in amplitude between VW and VCOMP. Operating on these large- amplitude, low noise synthesized signals allows the ISL6263D to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6263D has an error amplifier that allows the controller to maintain tight voltage regulation accuracy throughout the VID range from 0.7V to 1.0875V. Voltage Programming The output voltage VOUT is regulated to the SOFT pin voltage, VSOFT, which is determined by the DAC output and is programmed by the external three VID pins. Another two pins OFFSET0 and OFFSET1 incrementally provide +12.5mV and +25mV offset of the DAC output voltage, respectively. Table 1 shows the DAC output specification. Power-On Reset The ISL6263D is disabled until the voltage at the VDD pin has increased above the rising VDD power-on reset (POR) VDD_THR threshold voltage. The controller will become disabled when the voltage at the VDD pin decreases below the falling POR VDD_THF threshold voltage. Start-Up Timing Figure 4 shows the ISL6263D start-up timing. Once VDD has ramped above VDD_THR, the controller can be enabled by pulling the VR_ON pin voltage above the input-high threshold VVR_ONH. Approximately 100µs later, the soft-start capacitor CSOFT begins slewing to the designated VID set-point as it is charged by the soft-start current source ISS. The VOUT output voltage of the converter follows the VSOFT voltage ramp to within 10% of the VID set-point then counts 13 switching cycles, then changes the open-drain output of the PGOOD pin to high impedance. During soft-start, the regulator always operates in continuous conduction mode (CCM). Static Regulation The VOUT output voltage will be regulated to the value set by the VID inputs per Table 1. A true differential amplifier connected to the VSEN and RTN pins implements processor Kelvin sense for precise core voltage regulation at the GPU voltage sense points. The ISL6263D can accommodate DCR current sense or discrete resistor current sense. The DCR current sense uses the intrinsic series resistance of the output inductor, as shown in the application circuit of Figure 2. The discrete resistor current sense uses a shunt connected in series with the output inductor, as shown in the application circuit of Figure 3. In both cases the signal is fed to the non-inverting input of the current sense amplifier at the ISP pin, where it is measured differentially with respect to the output voltage of the converter at the VO pin and amplified. The voltage at the ICOMP pin minus the output voltage measured at the VO pin, is proportional to the total inductor current. This information is used for overcurrent protection and current monitoring. It is important to note that this current measurement should not be confused with the synthetic current ripple information created within the R3 modulator. When using inductor DCR current sense, an NTC compensation network is optional to compensate the positive temperature coefficient of the copper winding, thus maintaining the current sense accuracy. Processor Kelvin Voltage Sense The remote voltage sense input pins VSEN and RTN of the ISL6263D are to be terminated at the die of the GPU. Kelvin sense allows the voltage regulator to tightly control the processor voltage at the die, compensating for various resistive voltage drops in the power delivery path. VR_ON VSOFT/VOUT PGOOD 13 SWITCHING CYCLES ~100µs 90% FIGURE 4. ISL6263D START-UP TIMING |
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