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ISL6263CHRZ-T Datasheet(PDF) 11 Page - Renesas Technology Corp |
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ISL6263CHRZ-T Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 18 page  ISL6263C FN6745 Rev 1.00 Page 11 of 18 July 8, 2010 forcing the low-side MOSFET to operate as a synchronous rectifier. An improvement in light-load efficiency is achieved by allowing the converter to operate in diode-emulation mode (DEM) where the low-side MOSFET behaves as a smart- diode, forcing the device to block negative inductor current flow. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the source of the high-side MOSFET, or into the drain of the low-side MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the VSS pin. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the VSS pin. Negative inductor current occurs when the output DC load current is less than ½ the inductor ripple current. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. Efficiency can be further improved with a reduction of unnecessary switching losses by reducing the PWM frequency. The PWM frequency can be configured to automatically make a step-reduction upon entering DEM by forcing a step-increase of the window voltage VW. The window voltage can be configured to increase approximately 30%, 50%, or not at all. The characteristic PWM frequency reduction, coincident with decreasing load, is accelerated by the step-increase of the window voltage. The converter will enter DEM after detecting three consecutive PWM pulses with negative inductor current. The negative inductor current is detected during the time that the high-side MOSFET gate driver output UGATE is low, with the exception of a brief blanking period. The voltage between the PHASE pin and VSS pin is monitored by a comparator that latches upon detection of positive phase voltage. The converter will return to CCM after detecting three consecutive PWM pulses with positive inductor current. The inductor current is considered positive if the phase comparator has not been latched while UGATE is low. Because the switching frequency in DEM is a function of load current, very light load condition can produce frequencies well into the audio band. To eliminate this audible noise, an audio filter can be enabled that briefly turns on the low-side MOSFET gate driver LGATE approximately every 35µs. The DEM and audio filter operation are programmed by the AF_EN and FDE pins in conjunction with VID0:VID4 according to Table 2. Smooth mode transitions are facilitated by the R3 modulator, which correctly maintains the internally synthesized ripple current information throughout mode transitions. Current Monitor The ISL6263C features a current monitor output. The voltage between the IMON and VSS pins is proportional to the output inductor current. The output inductor current is proportional to the voltage between the ICOMP and VO pins. The IMON pin has source and sink capability for close tracking of transient current events. The current monitor output is expressed in Equation 1: Protection The ISL6263C provides overcurrent protection (OCP), overvoltage protection (OVP), and undervoltage protection (UVP), as shown in Table 3. Overcurrent protection is tied to the current sense amplifier. Given the overcurrent set point IOC, the maximum voltage at ICOMP pin VICOMP(max) (which is the voltage when OCP happens) can be determined by the current sense network (explained in “Inductor DCR Current Sense” on page 14 and “Resistor Current Sense” on page 15). During start-up, the ICOMP pin must fall 25mV below the OCSET pin to reset the overcurrent comparator, which requires (VICOMP(max) - VO) > 25mV. The OCP threshold detector is checked every 15µs and will increment a counter if the OCP threshold is exceeded, conversely the counter will be decremented if the load current is below the OCP threshold. The counter will latch an OCP fault when the counter reaches eight. The fastest OCP response for overcurrent levels that are no more than 2.5 times the OCP threshold is 120µs, which is eight counts at 15µs each. The ISL6263C protects against hard shorts by latching an OCP fault within 2µs for overcurrent levels exceeding 2.5 times the OCP threshold. The overcurrent threshold is determined by the resistor ROCSET between OCSET pin and VO pin. The value of ROCSET is calculated in Equation 2: For example, choose VICOMP(max) - VO = 80mV. ROCSET can use a 8.06kΩ resistor, according to Equation 2. UVP and OVP are independent of the OCP. If the output voltage measured on the VO pin is less than +300mV below the voltage on the SOFT pin for longer than 1ms, the controller will latch a UVP fault. If the output voltage measured on the VO pin is >195mV above the voltage on the SOFT pin for longer TABLE 2. DIODE EMULATION MODE and AUDIO FILTER GPU MODE (VID code) FDE AF_EN DEM STATUS VOLTAGE WINDOW AUDIO FILTER MODE 1 0- DISABLED NOM - 1- ENABLED 130% NOM - MODE 2 -0 ENABLED 150% NOM - 11 ENABLED 130% NOM - 01 ENABLED 130% NOM ENABLED VIMON VICOMP VO – 31 = (EQ. 1) ROCSET VICOMP max VO – 10 A ---------------------------------------------------- = (EQ. 2) |
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