ISL6265

FN6599 Rev 1.00

Page 8 of 24

May 13, 2009

ISL6265 Gate Driver Timing Diagram

OFFSET FUNCTION

OFS Pin Voltage For Droop Enabling

1.18

1.2

1.22

V

FB Pin Source Current

9.0

9.9

10.8

µA

OFS Pin Voltage Threshold for VFIX

Mode and No Droop Operation (Note 3)

-1.8

-

V

OFS Pin Voltage Threshold for SVI Mode

and No Droop Operation (Note 3)

-4.0

-

V

OFS Bias (Note 3)

1.8V < OFS < VCC

-

4.0

-

µA

LOGIC INPUTS

ENABLE Low Threshold

-

1.35

0.9

V

ENABLE High Threshold

2.0

1.6

-

V

ENABLE Leakage Current

Logic input is low

-1

0

-

µA

Logic input is high at 3.3V

-

0

1

µA

SVI INTERFACE

PWROK Input Low Threshold

-

0.65

0.8

V

PWROK Input High Threshold (Note 3)

-0.9

-

V

SVC, SVD Input HIGH (VIH)

1.05

0.87

-

V

SVC, SVD Input LOW (VIL)

-

0.68

0.45

V

Schmitt Trigger Input Hysteresis (Note 3)

-0.19

-

V

SVD Low Level Output Voltage

3mA Sink Current

-

0.1

0.285

V

SVC, SVD Leakage (Note 3)

EN = 0V, SVC, SVD = 0V

-

< -100

-

nA

EN = 5V, SVC, SVD = 1.8V

-

< -100

-

nA

DIFF AMP

Accuracy

VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V

-2

-

2

mV

NOTES:

3. Limits should be considered typical and are not production tested.

4. Limits established by characterization and are not production tested.

Electrical Specifications

at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production

tested. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX UNITS

PWM

UGATE

LGATE

1V

1V