ISL62773

FN8263 Rev 1.00

Page 10 of 37

Dec 16, 2015

37

UGATEX

High-side MOSFET gate driver portion of the programmable internal driver used for either Channel 3 of

the Core VR or Channel 1 of the Northbridge VR based on the configuration state selected by the

FCCM_NB resistor. Connect the UGATEX pin to the gate of the high-side MOSFET(s) for either Phase 3 of

the Core VR or Phase 1 of the Northbridge VR based on the configuration state selected.

38

PHASEX

Phase connection of the programmable internal driver used for either Channel 3 of the Core VR or

Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.

Current return path for the high-side MOSFET gate driver of the floating internal driver. Connect the

PHASEX pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the

output inductor of either Phase 3 of the Core VR or Phase 1 of the Northbridge VR based on the

configuration state selected.

39

LGATEX

Low-side MOSFET gate driver portion of floating internal driver used for either Channel 3 of the Core VR

or Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.

Connect the LGATEX pin to the gate of the low-side MOSFET(s) for either Phase 3 of the Core VR or

Phase 1 of the Northbridge VR based on the configuration state selected.

40

PWM2_NB

PWM output for Channel 2 of the Northbridge VR. Disabled when ISEN2_NB is tied to +5V.

41

FCCM_NB

Diode emulation control signal for Intersil MOSFET Drivers. When FCCM_NB is LOW, diode emulation at

the driver this pin connects to is allowed. A resistor from FCCM_NB pin to GND configures the PWM_Y

and floating internal gate driver [BOOTX, UGATEX, PHASEX, LGATEX pins] to support Phase 3 of the Core

VR and Phase 1 of the Northbridge VR. The FCCM_NB resistor value also is used to set the slew rate for

the Core VR and Northbridge VR.

42

PGOOD_NB

Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage. Pull

up externally to VDDP or 3.3V through a resistor.

43

COMP_NB

Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset

voltage and is used to set the switching frequency for the Core VR and Northbridge VR.

44

FB_NB

Output voltage feedback to the inverting input of the Northbridge controller error amplifier.

45

VSEN_NB

Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor

die.

46

ISUMN_NB

Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.

47

ISUMP_NB

Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge

VR.

48

ISEN1_NB

Individual current sensing for Channel 1 of the Northbridge VR. If ISEN2_NB is tied to +5V, this pin cannot

be left open and must be tied to GND with a 10kΩ resistor. If ISEN1_NB is tied to+5V, the Northbridge

portion of the IC is shutdown.

GND (Bottom Pad)

Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.

PIN NUMBER

SYMBOL

DESCRIPTION

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

ISL62773HRZ

ISL62773 HRZ

-10 to +100

48 Ld 6x6 QFN

L48.6x6B

ISL62773IRZ

ISL62773 IRZ

-40 to +85

48 Ld 6x6 QFN

L48.6x6B

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62773. For more information on MSL please see tech brief TB363.