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74LVC3G06 Datasheet(PDF) 7 Page - NXP Semiconductors |
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74LVC3G06 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 9397 750 14541 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 01 February 2005 7 of 15 Philips Semiconductors 74LVC3G06 Triple inverter with open-drain output 12. Dynamic characteristics [1] All typical values are measured at Tamb = 25 °C and nominal VCC. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; ∑(C L × VCC 2 × f o) = sum of the outputs. [3] The condition is VI = GND to VCC. Table 9: Dynamic characteristics GND = 0 V; see Figure 7 for test circuit. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +85 °C [1] tPLZ, tPZL propagation delay input nA to output nY see Figure 6 VCC = 1.65 V to 1.95 V 1.0 2.6 6.5 ns VCC = 2.3 V to 2.7 V 0.5 1.6 3.9 ns VCC = 2.7 V 1.0 2.2 4.2 ns VCC = 3.0 V to 3.6 V 0.5 2.0 3.4 ns VCC = 4.5 V to 5.5 V 0.5 1.4 2.9 ns CPD power dissipation capacitance per gate VCC = 3.3 V [2] [3] - 5.9 - pF Tamb = −40 °C to +125 °C tPLZ, tPZL propagation delay input nA to output nY see Figure 6 VCC = 1.65 V to 1.95 V 1.0 - 8.2 ns VCC = 2.3 V to 2.7 V 0.5 - 4.9 ns VCC = 2.7 V 1.0 - 5.3 ns VCC = 3.0 V to 3.6 V 0.5 - 4.3 ns VCC = 4.5 V to 5.5 V 0.5 - 3.7 ns |
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