FN9287 Rev 1.00

Page 24 of 25

November 2, 2007

ISL97652

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1). Cout, Cin, CB: get these components as close to

PGND1,2,3 as possible and use wide tracks on the top

PGND layer with no vias.

2). L1, D1, L2, D5: get these components as close to the

chip pins as possible (having observed 1/) and use wide

tracks on the top PGND layer with no vias.

3). Feedback resistor networks connected to FB, FBB, FBP,

FBN, POS1,2: keep tracks as short as possible (having first

observed 1/ and 2/). Routing on the SGND layer should be

used. Avoid routing this tracks under switching tracks on the

top surface.

4). All other components: keep all switching output tracks

(SW1,2, SWB1,2, CBOOT, DRVP, DRVN, VGHM, VFLK) on

the PGND layer shielded from adjacent tracks.

Evaluation PCB

A two layer evaluation PCB is available which follows the

above procedure and may be useful as a reference to guide

the PCB layout engineer. For example, the smoothing

capacitor positive rail to PVin does contain vias in series;

however, a small capacitor has been used directly at the

PVin pins which overcomes the ESR objection.