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HMN1288D Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part No. HMN1288D
Description  Non-Volatile SRAM MODULE 1Mbit (128K x 8-Bit), 32Pin-DIP, 5V
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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HMN1288D Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

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HANBit
HMN1288D
URL : www.hbe.co.kr
2
HANBit Electronics Co.,Ltd
Rev. 1.0 (June, 2002)
A0-A16 : Address Input
/CE : Chip Enable
Vss : Ground
DQ0-DQ7 : Data In / Data Out
/WE : Write Enable
/OE : Output Enable
VCC : Power (+5V)
NC : No Connection
FUNCTIONAL DESCRIPTION
The HMN1288D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by
the address inputs(A0-A16) defines which of the 131,072 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (access time) after the last address input signal is stable.
When power is valid, the HMN1288D operates as a standard CMOS SRAM. During power-down and power-up cycles, the
HMN1288D acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN1288D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs
are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge.
The HMN1288D provides full functional capability for Vcc greater than 4.5 V and write protects by 4.37 V nominal. Power-
down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD. When VCC falls
below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and
all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium
energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching
circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after Vcc exceeds 4.5 volts.
BLOCK DIAGRAM
PIN DESCRIPTION
DQ0-DQ7
A0-A16
/OE
/WE
/CE CON
Power
VCC
Lithium
Cell
128K x 8
SRAM
Block
/CE
Power – Fail
Control


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