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ISO224 Datasheet(PDF) 3 Page - Texas Instruments |
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ISO224 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 25 page 1 VCAP 8 VDD2 2 IN 7 OUTP 3 VDD1 6 OUTN 4 GND1 5 GND2 Not to scale 3 ISO224 www.ti.com SBAS738 – JUNE 2018 Product Folder Links: ISO224 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 5 Device Comparison Table PARAMETER ISO224B ISO224A Input offset voltage, VOS ±5 mV (max) ±50 mV (max) Input offset drift, TCVOS ±45 µV/°C (max) ±60 µV/°C (max) Gain error, EG ±0.3% (max) ±0.5% (max) Gain error drift, TCEG ±50 ppm/°C (max) ±60 ppm/°C (max) Input-referred noise 3.1 µV/ √Hz (typ) 4 µV/ √Hz (typ) Nonlinearity ±0.01% (max) ±0.02% (max) Output bandwidth, BW 275 kHz (typ) 175 kHz (typ) IN to OUTP, OUTN signal delay (50% – 50%) 2.1 µs (typ) 2.8 µs (typ) 6 Pin Configuration and Functions DWV Package 8-Pin SOIC Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 VCAP — Supply decoupling capacitor. Connect a 0.22-µF capacitor between this pin and the high-side analog ground. 2 IN I Analog input 3 VDD1 — High-side power supply, 4.5 V to 18 V. See the Power Supply Recommendations section for decoupling recommendations. 4 GND1 — High-side analog ground 5 GND2 — Low-side analog ground 6 OUTN O Inverting analog output 7 OUTP O Noninverting analog output 8 VDD2 — Low-side power supply, 4.5 V to 5.5 V. See the Power Supply Recommendations section for decoupling recommendations. |
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