Data Sheet

ADL5335

Rev. 0 | Page 13 of 16

THEORY OF OPERATION

BASIC STRUCTURE

The ADL5335 is an SPI controlled DGA. An integrated, on-chip

balun converts a 50 Ω differential RF input into a 50 Ω single-

ended RF output. The RF inputs and the RF output utilize

internal ac coupling capacitors.

The DGA core consists of a fixed gain amplifier and digitally

controlled attenuator. The amplifier has a gain of 12.0 dB. The

attenuator has a range of 0 dB to −8.0 dB with +0.5 dB steps and

uses a thermometer coding technique to eliminate transient

glitches during gain changes.

DIGITAL INTERFACE OVERVIEW

The ADL5335 digital section includes an enable pin (ENBL),

a fast attack pin (FA), and a SPI.

Serial Peripheral Interface (SPI)

The SPI uses the three following pins: the serial data

input/output (SDIO), the serial clock (SCLK), and the chip

select bar (CS).

The SPI data register consists of three bytes: one read/write bit

(R/W), 15 address bits (A14 to A0), two fast attack (FA)

attenuation step size bits (D7 and D6), and six gain control bits

(D5 to D0), as shown in Figure 24.

The gain code and fast attack attenuation step size bits are

controlled via Register Address 0x100. See Table 6 and Table 7,

respectively, for their truth tables.

Table 6. Gain Code Truth Table

6-Bit Binary Gain Code, Bits[D5:D0]

Gain (dB)

000000

+12.0

000001

+11.5

000010

+11.0

000011

+10.5

000100

+10.0

000101

+9.5

000110

+9.0

000111

+8.5

001000

+8.0

001001

+7.5

001010

+7.0

001011

+6.5

001100

+6.0

001101

+5.5

001110

+5.0

001111

+4.5

6-Bit Binary Gain Code, Bits[D5:D0]

Gain (dB)

010000

+4.0

010001

+3.5

010010

+3.0

010011

+2.5

010100

+2.0

010101

+1.5

010110

+1.0

010111

+0.5

011000

0

011001

−0.5

011010

−1.0

011011

−1.5

011100

−2.0

011101

−2.5

011110

−3.0

011111

−3.5

100000

−4.0

100001

−4.5

100010

−5.0

100011

−5.5

100100

−6.0

100101

−6.5

100110

−7.0

100111

−7.5

101000

−8.0

100011 to 111111

−8.0

Fast Attack (FA)

The fast attack feature allows the gain to be reduced from its

present setting by a predetermined step size. Four different

attenuation step sizes are available (see Table 7).

The FA pin controls fast attack mode. A logic high on the FA

pin results in an attenuation that is selected by Bits[D7:D6] in

the SPI register (Register Address 0x100).

Table 7. Fast Attack Attenuation Step Size Truth Table

6-Bit Binary Gain Code, Bits[D7:D6]

Step Size (dB)

00

−2

01

−4

10

−8

11

−16