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CS7622 Datasheet(PDF) 15 Page - Cirrus Logic |
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CS7622 Datasheet(HTML) 15 Page - Cirrus Logic |
15 / 36 page CS7622 DS322PP1 15 The CS7622 receives only the first 16 rising edges of the SCLK while SEN is low and then ignores any remaining SCLK and SDATI information. If SEN goes high before 16 SCLK pulses have been received, the CS7622 aborts the serial transfer. The first bit is the R/W bit. R/W = 1 identifies the transfer as a read. If (0), the transfer is a write. The next seven bits define the address. For write trans- fers, the second byte of the 16-bit packet contains the data byte. For read transfers, the CS7622 out- puts the read data on SDATO after accepting the address. Address and data are transferred MSB first. When not reading out data, the SDATO pin is not driven by the chip (Hi-Z state). The timing diagrams and specifications are shown in “Serial Interface Timing Specifications” on page 5 and Figures 1, 2, and 3 on page 5. 3.7 Input Timing for Sampling Clocks The input clocks CK_FT and CK_DT are used to set up the sampling times and also to generate the internal digital clock. These clocks need to be run- ning when processing pixels from the CCD, writing to the chip registers, or performing calibration (See Register Description of Operation Control 2 reg 05h bit 0 for the details of performaing a calibra- tion). The timing of these clocks is important to en- sure optimum settling times and sampling the correct value. CK_FT and CK_DT need to be non- overlapping pulses made as wide as possible to give long settling times. The falling edge of CK_FT should be close to the end of feedthrough while the falling edge of CK_DT should be close to the end of the data section of the CCD signal. See figure 15. Typical timing is given in table 2. Longer non-overlapping values for T1 and T4 will increase the recovery time, thus requiring a slower clock rate. Timing Parameter Typical Operating Values T1, T4 2 ns T2, T3 5 ns Table 2. |
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