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DS21455 Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS21455 Datasheet(HTML) 6 Page - Dallas Semiconductor |
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6 / 270 page  DS21455/DS21458 Quad T1/E1/J1 Transceivers 6 of 270 LIST OF FIGURES Figure 3-1. DS21458 Block Diagram ......................................................................................................................... 15 Figure 3-2. DS21455 Block Diagram ......................................................................................................................... 16 Figure 4-1. DS21455 Framer/LIU Interim Signals ..................................................................................................... 18 Figure 4-2. DS21458 Framer/LIU Interim Signals ..................................................................................................... 19 Figure 5-1. DS21455 Pin Diagram, 27mm BGA........................................................................................................ 39 Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA................................................................................................... 40 Figure 8-1. Programming Sequence.......................................................................................................................... 48 Figure 9-1. Clock Map ............................................................................................................................................... 52 Figure 14-1. Normal Signal Flow Diagram ................................................................................................................ 80 Figure 17-1. Simplified Diagram of Receive Signaling Path...................................................................................... 93 Figure 17-2.Simplified Diagram of Transmit Signaling Path.................................................................................... 100 Figure 21-1. CRC-4 Recalculate Method ................................................................................................................ 122 Figure 25-1. Basic Balanced Network Connections ................................................................................................ 158 Figure 25-2. Basic Unbalanced Network Connections ............................................................................................ 159 Figure 25-3. Typical Monitor Application ................................................................................................................. 160 Figure 25-4. CMI Coding ......................................................................................................................................... 163 Figure 25-5. Basic Interface..................................................................................................................................... 173 Figure 25-6. Protected Interface Using Internal Receive Termination .................................................................... 174 Figure 25-7. E1 Transmit Pulse Template............................................................................................................... 176 Figure 25-8. T1 Transmit Pulse Template ............................................................................................................... 176 Figure 25-9. Jitter Tolerance.................................................................................................................................... 177 Figure 25-10. Jitter Attenuation (T1 Mode).............................................................................................................. 177 Figure 25-11. Jitter Attenuation (E1 Mode) ............................................................................................................. 178 Figure 29-1. IBO Example ....................................................................................................................................... 201 Figure 30-1. DS21455 ESIB Group ......................................................................................................................... 203 Figure 30-2. DS21458 ESIB Group ......................................................................................................................... 204 Figure 34-1. T1 Transmit Data Flow ........................................................................................................................ 211 Figure 34-2. T1 Transmit Data Flow (continued)..................................................................................................... 212 Figure 34-3. E1 Transmit Data Flow........................................................................................................................ 213 Figure 34-4. E1 Transmit Data Flow (continued)..................................................................................................... 214 Figure 34-5. E1 Transmit Data Flow (continued)..................................................................................................... 215 Figure 35-1. JTAG Functional Block Diagram ......................................................................................................... 216 Figure 35-2. TAP Controller State Diagram............................................................................................................. 219 Figure 36-1. Receive Side D4 Timing...................................................................................................................... 228 Figure 36-2. Receive Side ESF Timing ................................................................................................................... 229 Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled)............................................................ 230 Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) ........................................... 231 Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................... 232 Figure 36-6. Transmit Side D4 Timing..................................................................................................................... 233 Figure 36-7. Transmit Side ESF Timing .................................................................................................................. 234 Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled)........................................................... 235 Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) .......................................... 236 |
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