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FM573-P Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part # FM573-P
Description  Nonvolatile Octal Latch/Register
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FM573-P Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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Ramtron
FM573/574
27 March 2001
3/10
Overview
Nonvolatile logic is a revolutionary product family
that simplifies the design of system control functions.
The FM573 is a transparent octal latch; the FM574 is
an octal D-type register. These products are unique
because the stored values also are retained in the
absence of power. They are pin and functionally
compatible with their industry standard CMOS
equivalents. Any change in the latched state
automatically
is
written
into
a
nonvolatile
ferroelectric latch. This function is possible due to the
fast write time and extremely high write endurance of
the underlying ferroelectric memory technology. A
new state becomes nonvolatile no more than 500 ns
(VDD=5V) after the write begins.
Users interface to a conventional latch rather than
directly
to
the
nonvolatile
latch.
Equivalent
ferroelectric nonvolatile latches shadow the user’s
latches. They offer a very high but not unlimited
number of write-cycles. Therefore, the internal state
machine writes to the nonvolatile latch only if the
latched state has changed in order to minimize the
actual number of nonvolatile write-cycles. This
determination is made independently for each bit.
Due to the short write-time and realistic power slew
rates, it is virtually impossible for the system to lose
power before the nonvolatile state is acquired.
Power Down Sequence
An internal power monitor blocks updates to the
nonvolatile latch when VDD is below VMIN (internal
voltage reference). The power supply monitor also
blocks write access to the user latch when VDD is
below VMIN. To guarantee a proper nonvolatile write
of the last value, state changes should cease tPDS
before VDD reaches VMIN. The VMIN threshold is low
enough that no special action may be needed in
systems with slow slew rates. For fast power supply
slew-rates or for systems that run down to relatively
low supply voltages, the user should employ some
form of low-VDD reset that trips above VMIN.
Power Up
The VMIN threshold is a critical parameter for several
aspects of product operations. On power-up, the
FM573/574 automatically restores the Qn outputs
(and internal latches) to the previously stored state.
This process begins as VDD rises to VMIN and is
completed tRES afterward. Thus for all practical
purposes, the nonvolatile values have been restored
as soon as the system logic is functional on power-
up.
After
the
restore
process,
the
latch
is
indistinguishable from its last state prior to power
down and operates normally.
This power up sequence occurs as follows. On
detection of a power-up, the internal nonvolatile latch
is read. This value is then placed on an internal
version of the Dn input. A single internal clock is
generated to cause the user latch to accept the
restored data. After this process is comp lete, the latch
provides normal user-controlled operation. Users
should not attempt to latch externally supplied data
prior to tPUH after VDD reaches VMIN. The following
diagram
illustrates
the
power-up
and
down
sequences.
Figure 2. Power Cycle Flow Chart
System VDD rises,
bandgap begins to function
VDD > VMIN?
Read nonvolatile
store
Yes
No
Read
complete?
Restore data to
user latch, drive
pins
Yes
No
Restore
complete?
No
Allow user access
to latch, normal
operation
Yes
VDD < VMIN
Block new writes to
NV-Latch, user latch
Complete NV-
writes in progress
No
Yes


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