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ICS87973DYI-147 Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS87973DYI-147 Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 10 page 87973DYI-147 www.icst.com/products/hiperclocks.html REV. A AUGUST 26, 2003 9 Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS 1.65V±5% -1.65V±5% CYCLE-TO-CYCLE JITTER OUTPUT SKEW tsk(o) V DDO 2 V DDO 2 Qy Qx STATIC PHASE OFFSET (DIFFERENTIAL) nCLK EXT_FB CLK t(Ø) ➤ V DD 2 (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t (Ø) mean = Static Phase Offset V CMR Cross Points V PP nCLK CLK GND V DD STATIC PHASE OFFSET (LVCMOS) ➤t(Ø) V DD 2 V DD 2 (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset CLK0, CLK1 EXT_FB V DD, V DDA, VDDO GND DIFFERENTIAL INPUT LEVEL QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB ➤ ➤ V DDO 2 V DDO 2 V DDO 2 tcycle n tcycle n+1 tjit(cc) = tcycle n –tcycle n+1 1000 Cycles Clock Outputs 0.8V 2V 2V 0.8V tR t F OUTPUT RISE/FALL TIME Pulse Width t PERIOD t PW t PERIOD odc = V DDO 2 QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB OUTPUT DUTY CYCLE/ PULSE WIDTH PERIOD |
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