NBSG53A datasheet(10/18 Pages) ONSEMI

Part #	NBSG53A

Description	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS

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NBSG53A

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Table 11. AC CHARACTERISTICS for QFN−16

VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V

−40

°C

25

°C

85

°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

fmax

Maximum Frequency

(See Figures 4, 6, 8, 10, and 11)

DFF

(See Figures 5, 7, 9, 10, and 11)

(Note 30)

DIV/2

8

10

8

10

8

10

GHz

tPLH,

tPHL

Propagation Delay to Output Differential

(Note 34)

CLK

→Q, Q

SEL

→Q, Q

R

→Q, Q DIN/2

DFF

150

160

215

195

215

190

280

270

285

280

375

345

150

160

215

195

215

190

280

270

285

280

375

345

150

160

215

195

215

190

280

270

285

280

375

345

ps

tSKEW

Duty Cycle Skew (Notes 31 and 33) DFF

5

20

5

20

5

20

ps

tJITTER

RMS Random Clock Jitter

fin v 8 GHz

(See Figures 4 and 6) (Note 30)

Peak−to−Peak Data Dependent Jitter

fin = 8 Gb/s

0.5

TBD

1

0.5

TBD

1

0.5

TBD

1

ps

VINPP

Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 32)

75

2600

75

2600

75

2600

mV

tr

tf

Output Rise/Fall Times (20% − 80%)

@ 1 GHz

Q, Q

(OLS = VCC)

(OLS = VCC − 0.4 V)

(OLS = VCC − 0.8 V, OLS = FLOAT)

**(OLS = VEE)

28

15

25

20

40

35

65

28

15

25

20

40

35

65

28

15

25

20

40

35

65

ps

ts

Setup Time

D

→CLK

30

14

30

10

30

13

ps

th

Hold Time

D

→CLK

25

12

25

7

25

0

ps

trr

Reset Recovery

DFF, DIV/2

40

9

40

12

40

10

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

30. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50

W to

VCC − 2.0 V. Input edge rates is 40 ps (20% − 80%).

31. See Figure 14. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.

32. VINPP (MAX) cannot exceed VCC − VEE (Applicable only when VCC − VEE < 2600 mV).

33. See Figure 10. Duty Cycle % vs. Frequency.

34. For all OLS Configuration.

**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.

***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70

°C and devices packaged in QFN−16 have

maximum ambient temperature specification of 85

°C.

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