Electronic Components Datasheet Search
Selected language     English  ▼
Advanced Search

              



Part Name


AD5263BRU200-REEL7 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD5263BRU200-REEL7
Description  Preliminary Technical Data
Download  6 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

   
 3 page
background image
PRELIMINARY TECHNICAL DATA
Quad +15V Digital Potentiometers
AD5263
08 AUG ’02, REV PrD
- 3 -
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (V
DD = +5V, VSS = -5V, VL = +5V,
VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12)
Input Clock Pulse Width
tCH,tCL
Clock level high or low
50
ns
Data Setup Time
tDS
20
ns
Data Hold Time
tDH
20
ns
CLK to SDO Propagation Delay13
tPD
RL = 1KΩ, CL < 20pF
1
150
ns
CS Setup Time
tCSS
20
ns
CS High Pulse Width
tCSW
40
ns
Reset Pulse Width
tRS
90
ns
CLK Fall to
CS Rise Hold Time
tCSH
0
ns
CS Rise to Clock Rise Setup
tCS1
10
ns
I2C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
fSCL
0
400
KHz
tBUF Bus free time between STOP & START
t1
1.3
µs
tHD;STA Hold Time (repeated START)
t2
After this period the first clock pulse is generated
0.6
µs
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
µs
tSU;STA Setup Time For START Condition t5
0.6
µs
tHD;DAT Data Hold Time
t6
0
0.9
µs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of both SDA & SCL signals
t8
300
ns
tR Rise Time of both SDA & SCL signals
t9
300
ns
tSU;STO Setup time for STOP Condition
t10
0.6
µs
NOTES:
1.
Typicals represent average readings at +25°C and VDD = +5V, VSS = -5V.
2.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+5V, VSS=-5V.
3.
VAB = VDD, Wiper (VW) = No connect
4.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
5.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6.
Guaranteed by design and not subject to production test.
7.
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8.
Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic.
9.
PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
10.
All dynamic characteristics use VDD = +5V, VSS = -5V, VL = +5V.
11.
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
12.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics
are measured using VL = +5V.
13.
Propagation delay depends on value of VDD, RL, and CL see applications text.
14.
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89mil x 105mil, 9,345sq. mil.




Html Pages

1  2  3  4  5  6 


Datasheet Download



Related Electronics Part Number

Part NumberComponents DescriptionHtml ViewManufacturer
BAR65-07Silicon RF Switching Diode Preliminary data Low loss low capacitance PIN-Diode Band switch for TV-tuners 1 2 3 Siemens Semiconductor Group
SEMB4PNP Silicon Digital Transistor Array Preliminary data 1 2 3 4 Infineon Technologies AG
SEMH4NPN Silicon Digital Transistor Array Preliminary data 1 2 3 4 Infineon Technologies AG
ELD-426EWATechnical Data Sheet 0.4 Dual Digit Displays 1 2 3 4 5 Everlight Electronics Co., Ltd
OPV230Technical Data 1 2 3 4 OPTEK Technologies
BAR81Preliminary data Silicon RF Switching Diode Design for use in shunt configuration High shunt signal isolation Low shunt insertion loss 1 2 3 Siemens Semiconductor Group
SEMB9PNP Silicon Digital Transistor Array Preliminary data 1 2 3 4 Infineon Technologies AG
SEMH7NPN Silicon Digital Transistor Array Preliminary data 1 2 3 4 Infineon Technologies AG
CSBLA1MTechnical Data of Ceramic Resonator 1 2 3 4 5 MoreList of Unclassifed Manufacturers
ELD-426GWATechnical Data Sheet 0.4 Dual Digit Displays 1 2 3 4 5 Everlight Electronics Co., Ltd

Link URL

Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl