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Package Thermal Resistance for RGZ (QFN) Package

(1) (2)

Package Thermal Resistance for ZVA (BGA) Package

(1)

RECOMMENDED OPERATING CONDITIONS

TIMING REQUIREMENTS

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

Airflow (lfm)

θ

θ

θ

(3)

ψ

0

29.9

22.4

1.5

0.2

150

24.7

0.2

250

23.2

0.2

500

21.5

0.3

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

Connected to GND with nine thermal vias (0,3 mm diameter).

(3)

θ

Airflow (m/s)

θ

θ

θ

(2)

ψ

0 m/s

53.9

28.3

38.6

0.7

1 m/s

49.8

0.7

2 m/s

48.5

0.8

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

θ

MIN

NOM

MAX

UNIT

3

3.3

3.6

Supply voltage

V

2.3

V

V

High-level output current LVCMOS (includes all status pins)

–8

mA

Low-level output current LVCMOS (includes all status pins)

8

mA

Input voltage range LVCMOS

0

3.6

V

Low-level input voltage LVPECL

V

High-level input voltage LVPECL

V

0.5

1.3

V

Common-mode input voltage LVPECL

1

V

Operating free-air temperature

–40

85

°C

(1)

(2)

of 150 mV.

over recommended ranges of supply voltage, load and operating free air temperature

PARAMETER

MIN

TYP

MAX

UNIT

PRI_REF/SEC_REF_IN REQUIREMENTS

0

200

MHz

4

ns

dutyREF

40%

60%

VCXO_IN, VCXO_IN REQUIREMENTS

0

2200

MHz

(1)

At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the

STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.

(2)

(3)

If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency

detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This

effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!

6