(

)

D

IN

OUT

OUT

P

V

V

I

=

-

´

GND PLANE

Represents via used for

application-specific connections

IN

GND

EN

NC

OUT

18

TLV741P

SBVS309 – JULY 2017

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Product Folder Links: TLV741P

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Copyright © 2017, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

11.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

Input and output capacitors must be placed as close to the device pins as possible. To improve AC performance

(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate

output capacitor ground connection must be connected directly to the device GND pin. High-ESR capacitors may

degrade PSRR performance.

11.2 Layout Examples

Figure 28. SOT-23 Layout Example

11.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in

the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves

the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in

Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The

addition of plated through-holes to heat-dissipating layers also improves the heat sink effectiveness.

in Equation 3:

(3)

Figure 29 shows the maximum ambient temperature versus the power dissipation of the TLV741P device. This

figure assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual

board thermal impedances vary widely. If the application requires high power dissipation, having a thorough

understanding of the board temperature and thermal impedances is helpful to ensure the TLV741P device does

not operate above a junction temperature of 125°C.