NB3H73113G datasheet(19/24 Pages) ONSEMI

Part #	NB3H73113G

Description	Programmable OmniClock Generator

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Manufacturer	ONSEMI [ON Semiconductor]

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NB3H73113G

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19

Figure 17. Simplified LVCMOS Output Structure

VDD

Drive Strength

selection

CLKx

Drive Strength

selection

LVDS Interface

Differential signaling like LVDS has inherent advantage

of common mode noise rejection and low noise emission,

and thus a popular choice for clock distribution in systems.

TIA/EIA−644 or LVDS is a standard differential,

point−to−point bus topology that supports fast switching

speeds and has the benefit of low power consumption. The

driver consists of a low swing differential with constant

current of 3.5 mA through the differential pair, and

generates switching output voltage across a 100

W

terminating resistor (externally connected or internal to the

receiver). Power dissipation in LVDS standard ((3.5 mA)2 x

100

W = 1.2 mW) is thus much lower than other differential

signalling standards.

A fan−out LVDS buffer (like ON Semiconductor’s

NB6N1xS and NB6L1xS) can be used as an extension to

provide clock signal to multiple LVDS receivers to drive

multiple point−to−point links to receiving node.

VDDO

Vin

+

_

CLK 1

CLK 0

RT

100

W

+

_

Vout

Iss

Figure 18. Simplified LVDS Output Structure with Termination

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NB3H73113G Datasheet(PDF) 19 Page - ON Semiconductor

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