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SCF5250CPV120 Datasheet(PDF) 4 Page - Motorola, Inc |
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SCF5250CPV120 Datasheet(HTML) 4 Page - Motorola, Inc |
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4 / 48 page  SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Introduction Freescale Semiconductor 4 space, a 16-bit data bus, Output Enable, and Read/Write signals. This interface implements an extended synchronous protocol that supports bursting operations. 1.2.9 Serial Audio Interfaces The SC5250 digital audio interface provides three serial Philips IIS/Sony EIAJ interfaces. One interface is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other two interfaces are 3-pin (1 bit clock, 1 word clock, 1 data in or out). The serial interfaces have no limit on minimum sampling frequency. Maximum sampling frequency is determined by maximum frequency on bit clock input. This is 1/3 the frequency of the internal system clock. 1.2.10 IEC958 Digital Audio Interfaces The SCF5250 has one digital audio input interface, and one digital audio output interface. The single output carries the consumer “c” channel. 1.2.11 Audio Bus The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. Each transmitter has a source select register. In addition to the audio interfaces, there are six CPU accessible registers connected to the audio bus. Three of these registers allow data reads from the audio bus and allow selection of the audio source. The other three register provide a write path to the audio bus and can be selected by transmitters as the audio source. Through these registers, the CPU has access to the audio samples for processing. Audio can be routed from a receiver to a transmitter without the data being processed by the core so the audio bus can be used as a digital audio data switch. The audio bus can also be used for audio format conversion. 1.2.12 CD-ROM Encoder/Decoder The SCF5250 is capable of processing CD-ROM sectors in hardware. Processing is compliant with CD-ROM and CD-ROM XA standards. The CD-ROM decoder performs following functions in hardware: • Sector sync recognition • Descrambling of sectors • Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors • Third-layer error correction is not performed The CD-ROM encoder performs following functions in hardware: • Sector sync recognition • Scrambling of sectors |
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