 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MC92604 Datasheet(PDF) 1 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
MC92604 Datasheet(HTML) 1 Page - NXP Semiconductors |
|
|
1 / 2 page  The MC92604 Dual Gigabit Ethernet transceiver is a 1.25 giga-baud, full-duplex, interface device that can be used to transmit data between chips across a board, through a backplane, or through cabling, as well as to interface to GBIC/SFP modules. It was designed with the intent to meet the requirements of IEEE Std. 802.3-2002®. The MC92604 is two parts in one. It may be configured as either a dual channel 1 gigabit backplane serializer/deserializer, SerDes, or it is a dual 1 gigabit GMII or TBI PHY for Ethernet 1000Base-X applications. The dual MC92604 may optionally be configured as a single channel transceiver with serial link redundancy. The device fully supports the MDIO interface defined in the above referenced standard. The MC92604 features transmit FIFOs and source-synchronous transmit clocks per channel to further simplify interfacing that will support many other non-Ethernet applications. And finally, IEEE Std 1149.1 JTAG boundary scan is added for board test support. The Gigabit Ethernet transceiver is carefully designed for low power consumption and is built upon the proven transceiver technology in the MC92600 and MC92602 Quad SerDes devices. The MC92604 transceiver is offered in a JEDEC standard 196 pin 15 mm body size package to provide excellent board density in applications with a large number of channels. Dual Gigabit Ethernet SerDes Transceiver MC92604 XLINK_x_P XLINK_x_N MEDIA XCVR_x_DISABLE XCVR_x_LBE RLINK_x_N RLINK_x_P CLK_OUT__[1:0] Transmitter Receiver FIFO FIFO Receive Interface Unit REF_CLK_B REF_CLK System PLL TDO TDI, TRST_B, TCK JTAG CONTROLLER MDIO CONTOLLER 2 3 6 8B10B Decoder 8B10B Decoder XMIT_x_ENABLE XMIT_x_DATA [7:0] XMIT_x_K/ERR XMIT_x_CLK RESET CONFIG_INPUTS MD_DATA MD_CLK BIST Two Transceivers x = A & B MD_ADR [4:2] MD_ENABLE RECV_x_DATA [7:0] RECV_x_K RECV_x_ERR RECV_x_DV RECV_x_CLK RECV_x_CLK_B CLK GEN LINK CONTROLLER MC92604 DUAL GIGABIT ETHERNET TRANSCEIVER BLOCK DIAGRAM (As a single with redundancy, only channel A is used.) Typical applications > High-density board applications for communications designs utilizing IEEE 802.3 protocol > High-speed data transfer applications in high-bandwidth backplane and chassis-to- chassis networking > PHY interface to Motorola C-port (C-3e or C-5e) network processors and Power QUICC III (MPC8560 or MPC8540) communications processors |
Similar Part No. - MC92604 |
|
Similar Description - MC92604 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
