TLK4250

QUAD 1.0 to 2.5 Gbps TRANSCEIVER

SWRS025 − APRIL 2004

1

POST OFFICE BOX 655303

Serializer/Deserializer

Operation

Output

Optical Converters

Initialization

Applications

From Low-Speed Reference

200 mV Min

Interconnect and Point-to-Point Data Link

PBGA Package

description

The TLK4250 device is a four-channel, multi-gigabit transceiver used in high-speed bidirectional point-to-point

data transmission systems. The four channels in the transceiver are configured as four separate links. The

transceiver supports an effective serial interface speed of 1.0 Gbps to 2.5 Gbps per channel, providing up to

2.25 Gbps of data bandwidth per channel.

The primary application of the transceiver is to provide high-speed I/O data channels for point-to-point baseband

data transmission over controlled impedance media of approximately 50

Ω. The transmission media can be a

printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer

depend on the attenuation characteristics of the media and the noise coupling to the environment.

The transceiver can also replace parallel data transmission architectures by providing a reduction in the number

of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the

receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an

optical link. The data is then reconstructed into its original parallel format. It offers significant power and cost

savings over current solutions, as well as scalability for higher data rate in the future.

The transceiver performs the data parallel-to-serial and serial-to-parallel conversions. The clock extraction

functions as a physical layer interface device. The serial transceiver interface operates at a maximum data rate

of 2.5 Gbps. Each transmitter latches 18-bit parallel data at a rate based on the supplied reference clock

(GTx_CLK). The 18-bit parallel data is internally encoded into 20 bits by framing the 18-bit data with start and

stop bits. The resulting 20-bit frame is then transmitted differentially at 20 times the reference clock (GTx_CLK)

rate.

The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting

20-bit wide parallel data to the recovered clock (Rx_CLK). It then extracts the 18 bits of data from the 20-bit wide

data resulting in 18 bits of parallel data at the receive data terminals (RDx[0:17]). This results in an effective data

payload of 0.9 Gbps to 2.25 Gbps (18 bits data x GTx_CLK frequency) per channel.

The transceiver provides an internal loopback capability for self-test purposes. Serial data from the serializer

is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical

interface.

Copyright

 2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.