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ADC12DL066CIVS Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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ADC12DL066CIVS Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 23 page ADC12DL066 Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference General Description The ADC12DL066 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog in- put signals into 12-bit digital words at 66 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on- chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance and a 450 MHz Full Power Bandwidth. Operating on a single 3.3V power supply, the ADC12DL066 achieves 10.7 effec- tive bits and consumes just 686 mW at 66 MSPS, including the reference current. The Power Down feature reduces power consumption to 75 mW. The differential inputs provide a full scale differential input swing equal to 2 times V REF with the possibility of a single- ended input. Full use of the differential input is recom- mended for optimum performance. The digital outputs from the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or two’s comple- ment. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL066 can be con- nected to a separate supply voltage in the range of 2.4V to the digital supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to ease the evalua- tion process. Features n Single +3.3V supply operation n Internal sample-and-hold n Outputs 2.4V to 3.3V compatible n Pin compatible with ADC12D040 n Power down mode n On-chip reference Key Specifications n Resolution 12 Bits n DNL ±0.5 LSB (typ) n SNR (f IN = 10 MHz) 66 dB (typ) n SFDR (f IN = 10 MHz) 81 dB (typ) n Data Latency 6 Clock Cycles n Power Consumption — Operating 686 mW (typ) — Power Down Mode 75 mW (typ) Applications n Ultrasound and Imaging n Instrumentation n Communications Receivers n Sonar/Radar n xDSL n Cable Modems n DSP Front Ends Connection Diagram 20055201 20040319 TRI-STATE® is a registered trademark of National Semiconductor Corporation. March 2004 © 2004 National Semiconductor Corporation DS200552 www.national.com |
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