CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator
input, a full-duplex UART with extended baud rate configuration, 256 bytes of internal RAM, 128 byte Spe-
cial Function Register (SFR) address space, and a byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 to 24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys-
Figure 1.3. Comparison of Peak MCU Execution Speeds
Clocks to Execute
Number of Instructions