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C8051F300 Datasheet(PDF) 28 Page - List of Unclassifed Manufacturers

Part # C8051F300
Description  Mixed Signal ISP Flash MCU Family
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C8051F300/1/2/3/4/5
28
Rev. 2.6
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Pin Number
Name
Type
Description
1
VREF /
P0.0
A In
D I/O or
A In
External Voltage Reference Input.
Port 0.0. See Section 12 for complete description.
2
P0.1
D I/O or
A In
Port 0.1. See Section 12 for complete description.
3
VDD
Power Supply Voltage.
4
XTAL1 /
P0.2
A In
D I/O or
A In
Crystal Input. This pin is the external oscillator circuit return
for a crystal or ceramic resonator. See Section 11.2.
Port 0.2. See Section 12 for complete description.
5
XTAL2 /
P0.3
A Out
D I/O
Crystal Input/Output. For an external crystal or resonator,
this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC network configurations.
See Section 11.2.
Port 0.3. See Section 12 for complete description.
6
P0.4
D I/O or
A In
Port 0.4. See Section 12 for complete description.
7
P0.5
D I/O or
A In
Port 0.5. See Section 12 for complete description.
8
C2CK /
/RST
D I/O
D I/O
Clock signal for the C2 Development Interface.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
9
P0.6 /
CNVSTR
D I/O or
A In
D I/O
Port 0.6. See Section 12 for complete description.
ADC External Convert Start Input Strobe.
10
C2D /
P0.7
D I/O
D I/O or
A In
Data signal for the C2 Development Interface.
Port 0.7. See Section 12 for complete description.
11
GND
Ground.


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