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C8051F300 Datasheet(PDF) 33 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 33 Page - List of Unclassifed Manufacturers |
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33 / 174 page  C8051F300/1/2/3/4/5 Rev. 2.6 33 5. ADC0 (8-Bit ADC, C8051F300/2) The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8- bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detec- tor are all configurable under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port pin, the Temperature Sensor output, or VDD with respect to any Port pin or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub- system is in low power shutdown when this bit is logic 0. Figure 5.1. ADC0 Functional Block Diagram AMUX0 + - X VDD ADC0CF 8-Bit SAR ADC 8 16 ADC0CN Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow Start Conversion 000 AD0BUSY (W) VDD ADC0GT ADC0LT 9-to-1 AMUX AD0WINT Temp Sensor 10-to-1 AMUX VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 GND 001 010 011 1xx CNVSTR Input Comb. Logic AMX0SL |
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