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C8051F300 Datasheet(PDF) 41 Page - List of Unclassifed Manufacturers

Part # C8051F300
Description  Mixed Signal ISP Flash MCU Family
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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C8051F300 Datasheet(HTML) 41 Page - List of Unclassifed Manufacturers

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C8051F300/1/2/3/4/5
Rev. 2.6
41
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2)
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2)
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
Bit2:
UNUSED. Read = 0b; Write = don’t care.
Bits1–0: AMP0GN1–0: ADC0 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
AD0SC4 AD0SC3
AD0SC2
AD0SC1
AD0SC0
AMP0GN1 AMP0GN0 11111000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBC
AD0SC
SYSCLK
CLKSAR
---------------------- 1
=
Bits7–0: ADC0 Data Word.
ADC0 holds the output data byte from the last ADC0 conversion. When in Single-ended
mode, ADC0 holds an 8-bit unsigned integer. When in Differential mode, ADC0 holds a 2’s
complement signed 8-bit integer.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBE


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