Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

C8051F300 Datasheet(PDF) 56 Page - List of Unclassifed Manufacturers

Part # C8051F300
Description  Mixed Signal ISP Flash MCU Family
Download  174 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC - List of Unclassifed Manufacturers

C8051F300 Datasheet(HTML) 56 Page - List of Unclassifed Manufacturers

Back Button C8051F300 Datasheet HTML 52Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 53Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 54Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 55Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 56Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 57Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 58Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 59Page - List of Unclassifed Manufacturers C8051F300 Datasheet HTML 60Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 56 / 174 page
background image
C8051F300/1/2/3/4/5
56
Rev. 2.6
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program-
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data stor-
age as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “17. C2 Interface” on page 169.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, macro assembler, debugger and pro-
grammer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compil-
ers are also available.
8.1.
Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1


Similar Part No. - C8051F300

ManufacturerPart #DatasheetDescription
logo
Silicon Laboratories
C8051F300 SILABS-C8051F300 Datasheet
1Mb / 176P
   Mixed Signal ISP Flash MCU Family
C8051F300-GDI SILABS-C8051F300-GDI Datasheet
210Kb / 9P
   8 kB Flash, 8-Bit ADC MCU Die in Wafer Form
C8051F300-GM SILABS-C8051F300-GM Datasheet
976Kb / 179P
   Mixed Signal ISP Flash MCU Family
C8051F300-GS SILABS-C8051F300-GS Datasheet
976Kb / 179P
   Mixed Signal ISP Flash MCU Family
C8051F300 SILABS-C8051F300_08 Datasheet
976Kb / 179P
   Mixed Signal ISP Flash MCU Family
More results

Similar Description - C8051F300

ManufacturerPart #DatasheetDescription
logo
Silicon Laboratories
C8051F80X SILABS-C8051F80X Datasheet
1Mb / 250P
   Mixed Signal ISP Flash MCU Family
C8051F80X SILABS-C8051F80X_14 Datasheet
1Mb / 251P
   Mixed Signal ISP Flash MCU Family
C8051F040-GQR SILABS-C8051F040-GQR Datasheet
2Mb / 328P
   Mixed Signal ISP Flash MCU Family
C8051F54X SILABS-C8051F54X Datasheet
3Mb / 276P
   Mixed Signal ISP Flash MCU Family
C8051F120 SILABS-C8051F120 Datasheet
2Mb / 356P
   Mixed Signal ISP Flash MCU Family
C8051F300 SILABS-C8051F300 Datasheet
1Mb / 176P
   Mixed Signal ISP Flash MCU Family
C8051F70X SILABS-C8051F70X Datasheet
1Mb / 290P
   Mixed Signal ISP Flash MCU Family
C8051F50X SILABS-C8051F50X Datasheet
2Mb / 312P
   Mixed Signal ISP Flash MCU Family
C8051F54X SILABS-C8051F54X_14 Datasheet
1Mb / 275P
   Mixed Signal ISP Flash MCU Family
C8051F124-GQR SILABS-C8051F124-GQR Datasheet
1Mb / 350P
   Mixed Signal ISP Flash MCU Family
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com