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C8051F300 Datasheet(PDF) 61 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 61 Page - List of Unclassifed Manufacturers |
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61 / 174 page  C8051F300/1/2/3/4/5 Rev. 2.6 61 8.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The CIP-51 memory organization is shown in Figure 8.2 and Figure 8.3. 8.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F300/1/2/3 implements 8192 bytes of this program memory space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x1FFF. Note: 512 bytes (0x1E00 - 0x1FFF) of this memory are reserved for factory use and are not available for user program storage. The C8051F304 implements 4096 bytes of reprogrammable Flash program memory space; the C8051F305 implements 2048 bytes of reprogramma- ble Flash program memory space. Figure 8.2 shows the program memory maps for C8051F300/1/2/3/4/5 devices. Figure 8.2. Program Memory Maps Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro- vides a mechanism for the CIP-51 to update program code and use the program memory space for non- volatile data storage. Refer to Section “10. Flash Memory” on page 87 for further details. FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 RESERVED 0x1000 0x0FFF C8051F304 (4k FLASH) C8051F300/1/2/3 (8k FLASH) FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 RESERVED 0x1E00 0x1DFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 RESERVED 0x0800 0x07FF C8051F305 (2k FLASH) |
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