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C8051F300 Datasheet(PDF) 84 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 84 Page - List of Unclassifed Manufacturers |
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84 / 174 page  C8051F300/1/2/3/4/5 84 Rev. 2.6 9.7. Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX operation is attempted above the user code space address limit. • A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted above the user code space address limit. • A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above the user code space address limit. The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the /RST pin is unaffected by this reset. 9.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol- lowing a software forced reset. The state of the /RST pin is unaffected by this reset. Table 9.1. User Code Space Address Limits Device User Code Space Address Limit C8051F300/1/2/3 0x1DFF C8051F304 0x0FFF C8051F305 0x07FF Table 9.2. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units /RST Output Low Voltage IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 0.6 V /RST Input High Voltage 0.7 x VDD V /RST Input Low Voltage 0.3 x VDD /RST Input Leakage Current /RST = 0.0 V 25 40 µA VDD Monitor Threshold (VRST) 2.40 2.55 2.70 V Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation 100 220 500 µs Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 5.0 µs Minimum /RST Low Time to Generate a System Reset 15 µs VDD Ramp Time VDD = 0 to VRST — — 1 ms |
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