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C8051F300 Datasheet(PDF) 94 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 94 Page - List of Unclassifed Manufacturers |
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94 / 174 page  C8051F300/1/2/3/4/5 94 Rev. 2.6 SFR Definition 11.1. OSCICL: Internal Oscillator Calibration SFR Definition 11.2. OSCICN: Internal Oscillator Control Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. On C8051F300/1 devices, the reset value is factory cali- brated to generate an internal oscillator frequency of 24.5 MHz. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value — Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB3 Bits7–5: UNUSED. Read = 000b, Write = don't care. Bit4: IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator is not running at programmed frequency. 1: Internal Oscillator is running at programmed frequency. Bit3: CLKSL: System Clock Source Select Bit. 0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits. 1: SYSCLK derived from the External Oscillator circuit. Bit2: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. Bits1–0: IFCN1-0: Internal Oscillator Frequency Control Bits. 00: SYSCLK derived from Internal Oscillator divided by 8. 01: SYSCLK derived from Internal Oscillator divided by 4. 10: SYSCLK derived from Internal Oscillator divided by 2. 11: SYSCLK derived from Internal Oscillator divided by 1. R/W R/W R/W R R/W R/W R/W R/W Reset Value — — — IFRDY CLKSL IOSCEN IFCN1 IFCN0 00010100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB2 |
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