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C8051F300 Datasheet(PDF) 99 Page - List of Unclassifed Manufacturers |
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C8051F300 Datasheet(HTML) 99 Page - List of Unclassifed Manufacturers |
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99 / 174 page  C8051F300/1/2/3/4/5 Rev. 2.6 99 12. Port Input/Output Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital resources as shown in Figure 12.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre- sponding Port latch, regardless of the Crossbar settings. The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 12.3 and Figure 12.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 12.1, SFR Definition 12.2, and SFR Definition 12.3 are used to select internal digital functions. All Port I/Os are 5 V tolerant (refer to Figure 12.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port0 Output Mode register (P0MDOUT). Complete Electrical Specifications for Port I/O are given in Table 12.1 on page 106. Figure 12.1. Port I/O Functional Block Diagram Figure 12.2. Port I/O Cell Block Diagram XBR0, XBR1, XBR2 Registers Digital Crossbar Priority Decoder SYSCLK 2 2 Highest Priority Lowest Priority P0 I/O Cells P0.0 P0.7 8 P0MDOUT, P0MDIN Registers SMBus UART T0, T1 2 4 PCA P0 Port Latch (P0.0-P0.7) 8 CP0 Outputs 2 GND /PORT-OUTENABLE PORT-OUTPUT PUSH-PULL VDD VDD /WEAK-PULLUP (WEAK) PORT PAD ANALOG INPUT Analog Select PORT-INPUT |
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