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K9K2G08U1A Datasheet(PDF) 11 Page - Samsung semiconductor |
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K9K2G08U1A Datasheet(HTML) 11 Page - Samsung semiconductor |
11 / 37 page 11 K9F1G08U0A K9F1G08R0A K9K2G08U1A FLASH MEMORY AC Timing Characteristics for Command / Address / Data Input NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low. 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 3. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A. Parameter Symbol Min Max Unit K9F1G08R0A K9F1G08U0A K9F1G08R0A K9F1G08U0A CLE setup Time tCLS*1 25 15 - - ns CLE Hold Time tCLH 10 5 - - ns CE setup Time tCS*1 35 20 - - ns CE Hold Time tCH 10 5 - - ns WE Pulse Width tWP 25 15 - - ns ALE setup Time tALS*1 25 15 - - ns ALE Hold Time tALH 10 5 - - ns Data setup Time tDS*1 20 15 - - ns Data Hold Time tDH 10 5 - - ns Write Cycle Time tWC 45 30 - - ns WE High Hold Time tWH 15 10 - - ns ALE to Data Loading Time tADL*2 100*2 100*2 -- ns AC Characteristics for Operation NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A. Parameter Symbol Min Max Unit K9F1G08R0A K9F1G08U0A K9F1G08R0A K9F1G08U0A Data Transfer from Cell to Register tR - - 25 25 µs ALE to RE Delay tAR 10 10 - - ns CLE to RE Delay tCLR 10 10 - - ns Ready to RE Low tRR 20 20 - - ns RE Pulse Width tRP 25 15 - - ns WE High to Busy tWB - - 100 100 ns Read Cycle Time tRC 50 30 - - ns RE Access Time tREA - - 30 20 ns CE Access Time tCEA - - 45 35 ns RE High to Output Hi-Z tRHZ - - 30 30 ns CE High to Output Hi-Z tCHZ - - 20 20 ns RE or CE High to Output hold tOH 15 15 - - ns RE High Hold Time tREH 15 10 - - ns Output Hi-Z to RE Low tIR 00 - - ns RE High to WE Low tRHW 100 100 - - ns WE High to RE Low tWHR 60 60 - - ns Device Resetting Time (Read/Program/Erase) tRST -- 5/10/500*1 5/10/500*1 µs |
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