Preliminary W78IE52

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5. BLOCK DIAGRAM

P3.0

~

P3.7

P1.0

~

P1.7

ALU

Port 0

Latch

Port 1

Latch

Timer

1

Timer

0

Timer

2

Port

1

UART

XTAL1

PSEN

ALE

Vss

Vcc

RST

XTAL2

Oscillator

Interrupt

PSW

Instruction

Decoder

&

Sequencer

Reset Block

Bus & Clock

Controller

SFR RAM

Address

Power control

256 bytes

RAM & SFR

Stack

Pointer

B

Addr. Reg.

Incrementor

PC

DPTR

Temp Reg.

T2

T1

ACC

Port 3

Latch

Port 4

Latch

Port

3

Port 2

Latch

P4.0

~

P4.3

Port

4

Port

0

Port

2

P2.0

~

P2.7

P0.0

~

P0.7

INT2

INT3

Watchdog

Timer

ROM

6. FUNCTIONAL DESCRIPTION

The W78IE52 architecture consists of a core controller surrounded by various registers, five general

purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports

111 different opcodes and references both a 64K program address space and a 64K data storage

space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide

control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.

RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.