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IDT71V2577YSA80BQ Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT71V2577YSA80BQ
Description  128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT71V2577YSA80BQ Datasheet(HTML) 9 Page - Integrated Device Technology

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6.42
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
9
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
(VDDQ = 2.5V)
NOTE:
1. The
LBO, TMS, TDI, TCK, and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while
ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
50
I/O
Z0 =50
4877d03
,
S ym bol
Param eter
Test Conditions
Min.
Max.
Unit
|ILI|
Inp ut Le ak ag e Curre nt
V DD = M ax ., V IN = 0V to V DD
___
5
µA
|ILI|
ZZ,
LBO and JTA G Inp ut Le akag e Curre nt(1)
V DD = M ax ., V IN = 0V to V DD
___
30
µA
|ILO|
O utp ut Le ak ag e Curre nt
V OUT = 0V to V DDQ , De v ice De se le cte d
___
5
µA
V OL
O utp ut Lo w Vo ltag e
IOL = +6m A , V DD = M in.
___
0.4
V
V OH
O utp ut Hig h Vo ltag e
IOH = -6m A , V DD = M in.
2.0
___
V
4877 tb l 0 8
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
IDD
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
255
200
210
180
190
mA
ISB1
CMOS Standby Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
30
35
30
35
mA
ISB2
Clock Running Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)
90
85
95
80
90
mA
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
30
30
35
30
35
mA
4877 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 2.5V
2ns
(VDDQ/2)
(VDDQ/2)
See Figure 1
4877 tbl 10
1
2
3
4
20 30 50
100
200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
4877d05
,


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