TDA9910 datasheet(7/21 Pages) PHILIPS

Part #	TDA9910

Description	12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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7 / 21 page

9397 750 14418

Objective data sheet

Rev. 02 — 9 December 2004

7 of 21

Philips Semiconductors

TDA9910

12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)

IIL

LOW-level input current

VIL = 0.8 V

-

5

-

µA

IIH

HIGH-level input current

VIH = 2.0 V

-

5

-

µA

Digital inputs: pins DEL0 and DEL1

VIL

LOW-level input voltage

DGND

-

0.3

× V

CCD

V

VIH

HIGH-level input voltage

0.7

× V

CCD

-VCCD

V

IIL

LOW-level input current

VIL = 0.8 V

-

80

-

µA

IIH

HIGH-level input current

VIH = 2.0 V

-

80

-

µA

Voltage controlled regulator output: pin CMADC

Vo(CM)

common mode output

voltage

IL =0mA

-

VCCA − 1.88 -

V

IL =2mA

-

VCCA − 1.91 -

V

Reference voltage input: pin FSIN [3]

VFSIN

full-scale ﬁxed voltage

-

VCCA − 1.84 -

V

IFSIN

input current

-

1

-

µA

Vi(p-p)

input voltage

(peak-to-peak value)

see Figure 5;

Vi =VIN − VINN;

Vi(CM) =VCCA − 1.91 V

1.5

1.9

2.0

V

Full-scale voltage controlled regulator output: pin FSOUT

Vo(ref)

1.9 V full-scale output

voltage

IL =IFSIN

-VCCA − 1.84 -

V

IL =2mA

-

VCCA − 1.87 -

V

Digital outputs: pins D11 to D0, IR and CCS

Output levels

VOL

LOW-level output voltage

IOL = 2 mA

DGND

-

DGND + 0.5

V

VOH

HIGH-level output voltage IOH = −0.4 mA

VCCO − 0.5 -

VCCO

V

IOZ

output current in 3-state

output level between

0.5 V and VCCO

−20

1

+20

µA

Timing [4]

td(s)

sampling delay time

CL = 10 pF

-

0.2

-

ns

th(o)

output hold time

CL = 10 pF

-

4

-

ns

td(o)

output delay time

CL = 10 pF

-

5

-

ns

3-state output delay

tdZH

enable HIGH

-

3

-

ns

tdZL

enable LOW

-

5

-

ns

tdHZ

disable HIGH

-

8

-

ns

tdLZ

disable LOW

-

5

-

ns

Clock timing inputs: pins CLK and CLKN

fCLK(min) minimum clock frequency

-

8

Msample/s

fCLK(max) maximum clock frequency duty cycle 45 % to

65 %

80

-

Msample/s

tCLKH

clock pulse width HIGH

fi = 175 MHz

5.6

-

ns

tCLKL

clock pulse width LOW

fi = 175 MHz

5.6

-

ns

Table 5:

Characteristics …continued

VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C

to +85

°C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN =VCCA1 − 1.77 V; Vi(CM) =VCCA1 − 1.85 V; typical values measured at

VCCA =VCCD = 5 V, VCCO = 3.3 V, Tamb =25 °C and CL = 10 pF; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Test [1] Min

Typ

Max

Unit

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