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W79E648 Datasheet(PDF) 19 Page - Winbond |
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W79E648 Datasheet(HTML) 19 Page - Winbond |
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19 / 80 page  Preliminary W79E648 Publication Release Date: 05/31/2004 - 19 - Revision A1 Software Reset Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFlash after time out. Port 2 Bit: 7 6 5 4 3 2 1 0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 Mnemonic: P2 Address: A0h P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. Port 4 Chip-select Polarity Bit: 7 6 5 4 3 2 1 0 P43INV P42INV P42INV P40INV - - - PUP0 6.1.1 Mnemonic: P4CSIN Address: A2h P4xINV: The active polarity of P4.x when set it as chip-select signal. High = Active High. Low = Active Low. PUP0: Enable Port 0 weak pull up. Port 4 Bit: 7 6 5 4 3 2 1 0 - - - - P4.3 P4.2 P4.1 P4.0 Mnemonic: P4 Address: A5h P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups. Port 4 can not use bit-addressable instruction (SETB or CLR). Interrupt Enable Bit: 7 6 5 4 3 2 1 0 EA ES1 ET2 ES ET1 EX1 ET0 EX0 Mnemonic: IE Address: A8h EA: Global enable. Enable/disable all interrupts. ET2: Enable Timer 2 interrupt. ES: Enable Serial Port 0 interrupt. ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt EX0: Enable external interrupt 0 |
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